Commit Graph

54281 Commits

Author SHA1 Message Date
Mike Banon 9faf74ca96 tint: update the tint build system to fix the download/patch errors
Restore the tint build system compatibility with the current version
of buildgcc script while preserving the backwards compatibility.

Change-Id: I45d3454b4527ee81c3927a5b3da2e9067c530fb0
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76819
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-08 16:02:31 +00:00
Fabian Groffen 6230d26ad1 mb/asrock/b75pro3-m: Drop destructive GPIO settings
Without setting these GPIO bits, you /can/ power on your board after
powering it down again.  This includes after cutting the power.
The only way to recover from this is to pull the CMOS battery and cut
the power for 15mins.  Then make sure you don't do this GPIO trickery or
you end up with the same state of basically an unresponsive "dead"
mainboard.  So flash the chip before you pull the battery.

One small workaround I found when you like to flash from the system, is
to press the power button with 1 second after you enable power to the
board.  In this small timeframe, apparently the superio chip didn't
intialise/restore/gets set with the settings that make it never want to
power on again.  The other workaround is to connect the appriopriate
pins on the ATX power connector to force power to the mainboard.

Signed-off-by: Fabian Groffen <grobian@gentoo.org>
Change-Id: I4c9df200ba3ec5f315ad3d184588551d29fa68ce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75212
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-08 16:02:01 +00:00
Elyes Haouas eb23fbeab0 vendorcode/cavium: Use C99 flexible arrays
Use C99 flexible arrays instead of older style of one-element or
zero-length arrays.
It allows the compiler to generate errors when the flexible array does
not occur at the end in the structure.

Change-Id: I19c029968584fedbb6749e66c7ea2f74a7d580f4
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76811
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-08 16:01:08 +00:00
Matt DeVillier dadb248333 mb/google/poppy/rammus: Fix jack detect GPIO configuration
Copy jack detect GPIO config of NAMI variant, which uses the same
codec for the external jack/mic. The internal pull-up isn't needed,
and fixes issue of high CPU usage under Windows.

TEST=build/boot google/rammus, verify jack detect functional under
both Win11 and Linux 6.x, no high CPU usage from excessive interrupts.

Change-Id: Ifbe23a6b33343e54b43879a8971c7cb6475cf1f0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76947
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-08 14:03:29 +00:00
Tony Huang 007547a553 mb/google/nissa/var/yavilla: Update eMMC DLL settings
Update eMMC DLL settings to prevent eMMC initialization error

BUG=b:290567342
TEST=warm/cold reboot stress test 2500 times pass

Change-Id: I418836ec3e2d2221c219eae35e2b22aeaacce4a5
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76823
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jamie Chen <jamie.chen@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
2023-08-08 13:17:25 +00:00
Kun Liu 961a88a115 mb/google/rex/var/screebo: Change sdcard clk from 7 to 6
Update firmware to reflect schematics change for SD Card CLKSRC
from 7 to 6 for EVT board revision

BUG=b:291051683
TEST=emerge-rex coreboot

Change-Id: I3347f739650458c833d5a825742cf1d663853cc5
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77023
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-08 10:14:20 +00:00
Nico Huber fdb3d07502 doc/forums: Update Matrix channel link
Channel portalling has been disabled for the matrix.org-libera.chat
bridge[1]. Hence, we created a new Matrix channel #coreboot:matrix.org
(that is plumbed to the IRC channel).

[1] https://libera.chat/news/matrix-deportalling

Change-Id: I896bfed71790988503dc8229fe9b34e175046dbf
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76864
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-08 10:09:14 +00:00
Kyösti Mälkki 88decca14f ACPI: Add helper fill_fadt_extended_pm_io()
Once platform code has filled in the (legacy) ACPI PM register
map, added function will fill in the extended entries in FADT.

TEST=samsung/lumpy and amd/mandolin FADT stays unchanged.

Change-Id: I90925fce35458cf5480bfefc7cdddebd41b42058
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74913
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-08 06:51:03 +00:00
Michał Żygowski d99de5db5b mainboard/protectli/vault_cml: Switch to IT8784E
The first platform samples came with IT8786E. The production units
switched to IT8784E in the final design.

Change the code to use IT8784E and reflect the proprietary firmware
configuration of the SIO chip.

TEST=Boot Ubuntu 22.04 on Protectli VP4670 (vault_cml) and dump the
configuration with superiotool and compare the configuration with
proprietary firmware.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I5dc6669b592484e445c8c4bbe95d73f0a9f0392e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74175
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-08-07 21:29:02 +00:00
Michał Żygowski 6503474efe superio/ite: Add IT8784E support
IT8784E is basically a IT8786E stripped from serial ports 3-6.

The patch creates a chip directory for IT8784E used by
protectli/vault_cml platforms.

TEST=Boot Ubuntu 22.04 on Protectli VP4670 (vault_cml) and dump the
configuration with superiotool and compare the configuration with
proprietary firmware.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ibe01358611f3ce3f155ddb01a7d177a3ff75765e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-07 21:27:38 +00:00
Stanley Wu 547d907b90 mb/google/dedede/var/boxy: Update power limits
Add ramstage.c in Makefile.inc and update boxy power limits in
Boxy ramstage.c.

BUG=b:290293153
TEST=emerge-dedede coreboot and check psys and PLx value on boxy

Change-Id: I4257dab358f066ebd13b6f251e8a5258a72fbd39
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76877
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-07 17:34:02 +00:00
Patrick Georgi bead4ed4db Documentation: Add section on how the project responds to legal threats
Threatening or initiating legal action against the maintainers of our
infrastructure or projects (all projects hosted on our infrastructure)
is a huge stressor to those maintainers.

To underline that severity, such threats or action will lead to an
immediate ban from our infrastructure as agreed on the leadership
meeting of 2023-05-31.

There may be legitimate legal action to take in certain cases, and
it's always possible to unban people, but given the severity provide
warning that we'll opt for a "ban first, sort out later" approach.

Change-Id: Ifa865487dc81ed3797fe60e5cef737c57dd85fea
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75554
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2023-08-07 11:59:09 +00:00
Keith Hui 863d3eb935 abuild: Fix board variant handling
Problem:
Me: $ util/abuild/abuild -t asus/p2b -b p2b-ls
abuild: No such target: asus/p2b, variant: p2b-ls

Cause: We identify boards and variants using path names in tree, so
I type in the test command above. abuild identifies all board variants
the Kconfig way, in all caps and all underscores.

Result: Expectation gap and abuild can't find anything where we expect
it to. All variants with a hyphen in their names are affected.

Fix: Add a substitution to replace hyphens with underscores.

Test: I get my abuild with the command above, even a variant-specific
test config works.

Change-Id: I10d5b471dac41c50a85c4a309ec561b02687bb9a
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41918
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-08-06 19:47:33 +00:00
Yidi Lin db95b24c74 soc/mediatek/mt8188: Support ARM arch timer
Use ARM architectual timer by initializing frequency to 13 MHz. Since
system timer is the source of the architectual timer, we also call
`timer_prepare` in `init_timer`.

BUG=b:229800119
TEST=run `suite:faft_bios` to verify the firmware stability.
     check timestamps by cbmem.

Cq-Depend: chromium:4747539
Change-Id: I8b1348044e4c92984510604b7f61611e13284d86
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76919
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-06 19:44:11 +00:00
Matt DeVillier a0ab63e4b6 3rdparty/blobs: update submodule pointer
Pull in commit adding signed verstage files for Google mainboards
zork, guybrush, and skyrim.

Change-Id: Ia3024622a622285b7b2a1f4eef88cf0e2927424e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-08-06 19:38:25 +00:00
Won Chung 063dfc2944 mb/google/brya: Add DRIVERS_GFX_GENERIC to BRYA by default
All boards based on brya will have GFX devices to represent DRM
connectors in the kernel's /sys/class/drm/.

There should be no functional impact with or without this patch.

BUG=b:277629750
TEST=emerge-brya coreboot

Change-Id: I11afa9e8a1c8bf9f57bf6d195f07531182bd36f1
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76873
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-08-06 19:37:50 +00:00
Martin Roth 2571ecb890 device, soc: Add SPDX license headers to Makefiles
To help identify the licenses of the various files contained in the
coreboot source, we've added SPDX headers to the top of all of the
.c and .h files. This extends that practice to Makefiles.

Any file in the coreboot project without a specific license is bound
to the license of the overall coreboot project, GPL Version 2.

This patch adds the GPL V2 license identifier to the top of all
makefiles in the device and soc directories that don't already have an
SPDX license line at the top.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I89c05c7c1c39424de2e3547c10661c7e3f58b8f7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76951
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
2023-08-06 19:34:05 +00:00
Martin Roth 8ebd8cc348 mainboard: Add SPDX license headers to Makefiles
To help identify the licenses of the various files contained in the
coreboot source, we've added SPDX headers to the top of all of the
.c and .h files. This extends that practice to Makefiles.

Any file in the coreboot project without a specific license is bound
to the license of the overall coreboot project, GPL Version 2.

This patch adds the GPL V2 license identifier to the top of all
makefiles in the mainboard directory that don't already have an SPDX
license line at the top.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ic451e68b1ad9ccdf34484dd98bd7fca7e177ef22
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68982
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-08-06 19:28:50 +00:00
Martin Roth 8324fe9211 drivers: Add SPDX license headers to Makefiles
To help identify the licenses of the various files contained in the
coreboot source, we've added SPDX headers to the top of all of the
.c and .h files. This extends that practice to Makefiles.

Any file in the coreboot project without a specific license is bound
to the license of the overall coreboot project, GPL Version 2.

This patch adds the GPL V2 license identifier to the top of all
makefiles in the drivers directory that don't already have an SPDX
license line at the top.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I8442bc18ce228eca88a084660be84bcd1c5de928
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68980
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-08-06 19:27:36 +00:00
Martin Roth f6ca89c224 cpu: Add SPDX license headers to Makefiles
To help identify the licenses of the various files contained in the
coreboot source, we've added SPDX headers to the top of all of the
.c and .h files. This extends that practice to Makefiles.

Any file in the coreboot project without a specific license is bound
to the license of the overall coreboot project, GPL Version 2.

This patch adds the GPL V2 license identifier to the top of all
makefiles in the cpu directory that don't already have an SPDX
license line at the top.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I3033f2a9eebc75220f7666325857b3ddd60c8f75
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68979
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-08-06 19:26:55 +00:00
Matt DeVillier 8ec426859f mb/google/brya: select ENABLE_TCSS_USB_DETECTION
Select ENABLE_TCSS_USB_DETECTION for non-ChromeOS builds, to enable
booting from TCSS USB-C ports.

TEST=build/boot google/banshee, verify able to boot from all USB ports
using edk2 payload.

Change-Id: I998cc4a40950f43b4c511ead93ccc02c56c8367c
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76945
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-06 19:26:26 +00:00
Matt DeVillier 11b0ba00b4 mb/google/volteer: select ENABLE_TCSS_USB_DETECTION
Select ENABLE_TCSS_USB_DETECTION for non-ChromeOS builds, to enable
booting from TCSS USB-C ports.

TEST=build/boot google/drobit, verify able to boot from USB ports using
edk2 payload.

Change-Id: Ic6ab84dd5d1b980296eac043917d2cc7f14a5536
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-08-06 19:26:05 +00:00
CoolStar 9c7433ec55 soc/intel/common/tcss: Configure USB-C ports with attached devices
Inspect all type-C USB ports, check if there is a USB device attached,
and if so, send the connection request to the PMC. This allows for any
attached USB2/USB3 devices to be used for booting by the payload.

Since this functionality is only needed by ChromeOS devices with TCSS
running upstream coreboot, introduce a new Kconfig to guard its use.
Boards needing it will select it in subsequent commits.

TEST=tested with rest of patch train

Change-Id: I69522dbcc8cae6bbf41659ae653107d0e031c812
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72909
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-06 19:25:34 +00:00
Matt DeVillier b33778e71f soc/intel/common/block/tcss: Fix printk formatting
Variable 'i' is unsigned, so use %zu vs %zd.

Change-Id: I5f5b28796b30285e81a94c37e686a9e763cab204
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76943
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-06 19:15:01 +00:00
Elyes Haouas 13b2427f5e payloads/U-Boot: Upgrade from U-Boot "v2021.07" to "v2023.07"
U-Boot v2023.07 was released on Mon 10 July 2023.
https://source.denx.de/u-boot/u-boot/-/blob/master/doc/develop/release_cycle.rst#id5

Change-Id: Ie1c6f83bd12e959c29fad1b121c85eb0cf898e24
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-08-05 23:00:20 +00:00
Jeremy Compostella d86260a134 commonlib/fsp_relocate: Fix pe_relocate() return value on success
Similarly to te_relocate(), on success pe_relocate() should return 0.
It has never been an issue so far as pe_relocate() return value is not
tested.

Change-Id: I8e531662952d12e1f0ffa34042dab778ea602bfc
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76891
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-08-05 16:12:37 +00:00
Tim Crawford 1d3e6eba02 mb/system76: Enable C10 reporting on systems using eSPI
Report CPU C10 state over eSPI so that the EC can use Virtual Wires to
detect if PECI can be used.

Change-Id: I301361f35caee8ba1c3fd9227219603897add92b
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76910
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-05 16:09:27 +00:00
Tim Crawford c9f99e5632 mb/system76/cml-u: Fix inclusion of romstage.c
When lemp9 was converted to a variant in CB:64528, the Makefile was not
updated to handle the variant-specific `romstage.c`. This, as would be
expected, caused memory init errors and broke boot on CML-U boards.

Tested lemp9 boots to payload again.

Fixes: 5b7b04c938 ("mb/system76/cml-u: Convert lemp9 to a variant")
Change-Id: Ibc11d69a1662df653e6553421d67a9cd1b1d03e2
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76871
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
2023-08-05 16:07:56 +00:00
Reka Norman a96b5ea30c mb/google/dedede: Enable wake from S0ix on EC_HOST_EVENT_HANG_DETECT
BUG=b:279097356
TEST=On dibbi:
- flash OS 15449.0.0 (where suspend is broken due to b:274531972)
- run `suspend_stress_test --count=1 --suspend_max=30 --suspend_min=28`
- check the AP wakes up immediately when the EC detects a sleep hang

Change-Id: I24a2aa5de1f76e6dd1c1ce726b648583756e5e55
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76938
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-05 16:06:31 +00:00
Stanley Wu 4c68d8467a mb/google/dedede/var/boxy: Add power limits for N4500/N5100
Add PLx from JSL PDG(ID: 613095) in boxy devicetree.

BUG=b:290293153
TEST=emerge-dedede coreboot and read correct value on boxy CPU log:
     CPU TDP = 6 Watts, CPU PL4 = 60 Watts

Change-Id: I7b063dc235fb714ba47eb620b914f2f9e92a2715
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76876
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-05 16:05:20 +00:00
Yuchen He 1e67adbc73 src/*/post_code.h: Change post code prefix to POSTCODE
The prefix POSTCODE makes it clear that the macro is a post code.
Hence, replace related macros starting with POST to POSTCODE and
also replace every instance the macros are invoked with the new
name.

The files was changed by running the following bash script from the
top level directory.

header="src/soc/amd/common/block/include/amdblocks/post_codes.h \
	src/include/cpu/intel/post_codes.h \
	src/soc/intel/common/block/include/intelblocks/post_codes.h"

array=`grep -r "#define POST_" $header | \
	tr '\t' ' ' | cut -d ":" -f 2 | cut -d " " -f 2`

for str in $array; do
	splitstr=`echo $str | cut -d '_' -f2-`
	grep -r $str src | cut -d ':' -f 1 | \
		xargs sed -i'' -e "s/$str/POSTCODE_$splitstr/g"
done

Change-Id: Id2ca654126fc5b96e6b40d222bb636bbf39ab7ad
Signed-off-by: Yuchen He <yuchenhe126@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76044
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-05 16:04:46 +00:00
Jamie Chen 71b8ee0da4 mb/google/nissa/var/craaskov: Add wifi sar table
Add wifi sar table for craaskov

BUG=b:290739538
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot chromeos-bootimage

Change-Id: Ib21f674b6749e125bf76a196902c994bfac15e65
Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76576
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-05 16:03:58 +00:00
Sukumar Ghorai c5a7d604c8 mb/google/rex: enable d3hot for storage devices
_DSD "StorageD3Enable" property is needs to be set under the root
port in the DSDT or SSDT. The ACPI _DSD method is the preferred way
to opt D3hot support for storage devices.

This also bypasses the low LTR from SSD that blocking S0i2.2
LTR/latency SoC requirement.

Name (_DSD, Package () {
    ToUUID("5025030F-842F-4AB4-A561-99A5189762D0"),
        Package () {
            Package (2) {"StorageD3Enable", 1},
            // 1 - Enable; 0 - Disable
        }
    }
)

BUG=b:289028958
TEST=Check code compiles & boot rex, and verify the "StorageD3Enable"
SSDT entry.

Change-Id: I19decc2706954e73bc28fc2d9c3c4d18d2c384b7
Signed-off-by: Kangheui Won <khwon@chromium.org>
Signed-off-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76835
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-05 16:03:37 +00:00
Rex Chou 684eca7dd2 mb/google/nissa/var/craaskov: Configure the external V1p05/Vnn/VnnSx
This patch configures external V1p05/Vnn/VnnSx rails for Craaskov
to follow best practices for power savings – untested though.

* Enable the external V1p05, Vnn, VnnSx rails in S0i1, S0i2, S0i3, S3,
  S4, S5 , S0 states.
* Set the supported voltage states.
* Set the voltage for v1p05 and vnn.
* Set the ICC max for v1p05 and vnn.

BUG=b:290165011
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot

Change-Id: Ibaf6a285788e26688d3d42691ab40052ef6d6cdb
Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76926
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-05 16:03:11 +00:00
Van Chen 8c77e58cd6 mb/google/nissa/var/craaskov: Add DPTF parameters
The DPTF parameters were verified by the thermal team.
Based on thermal table in 290705146#comment11.
Set "tcc_offset" = "8"

BUG=b:290705146
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot chromeos-bootimage

Change-Id: I2d9e1ad2e2fa98757d76578956101a482073885e
Signed-off-by: Van Chen <van_chen@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76712
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-05 16:03:04 +00:00
Matt DeVillier 5a53c4ddaf mb/google/glados: use acpi_is_wakeup_s3() vs FSP UPD
To be consistent with other boards setting the keyboard backlight at
boot.

Change-Id: I40d8ebe468a967f0dfe1e82bff9c63f1986699c7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76942
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-05 16:01:51 +00:00
Matt DeVillier e4f7c8fce8 mb/google/eve: Use keyboard backlight for proof-of-life at boot
This feature was originally present and then dropped, but turns out
that users prefer it. Set the backlight to 50% in romstage, back to
zero in ramstage; skip enabling on the S3 resume path.

TEST=build/boot google/eve, verify keyboard backlight turns on/off
as expected.

Change-Id: I33af888d614010538f69512bbd052ed2b83fcaa5
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76803
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-08-05 16:01:41 +00:00
Matt DeVillier 94ad304451 mb/google/rambi: Fix built-in audio under Windows
Move the jack detect GpioInt resources under the codec (where they
belong), but also leave a copy under LPEA for since the Linux drivers
(incorrectly) require them there. Add pin list for Windows' SST driver.

Adapted from the Intel ValleyView edk2 ACPI reference code.

TEST=build/boot Win11, Linux on google/swanky; verify audio functional
OOTB under Linux, under Windows with coolstar's drivers.

Change-Id: I51c07013fc20f07d2fd3639f7fbc2af0e0e490a0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76795
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
2023-08-05 16:01:09 +00:00
Matt DeVillier 1b67362971 mb/google/cyan: Adjust ACPI for Maxim audio
- add HRV and GpioIO for coolstar's windows drivers
- fix interrupt type for TI jack detect switch

TEST=build/boot Win11, Linux on google/cyan; verify audio working
OOTB under Linux, under Windows with coolstar's audio drivers.

Change-Id: I6bf6bb9e9989ca8f42436800666d95dd05799838
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76800
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-08-05 16:00:50 +00:00
Elyes Haouas ce61679c69 sb/intel/lynxpoint/Kconfig: Remove SOUTH_BRIDGE_OPTIONS
Remove dummy SOUTH_BRIDGE_OPTIONS.

Change-Id: Ic2f10ef03844ff55addfa27035b54971ac41dbc9
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76949
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-08-05 07:26:09 +00:00
Elyes Haouas 254a7c0f81 sb/intel/ibexpeak/Kconfig: Remove SOUTH_BRIDGE_OPTIONS
Remove dummy SOUTH_BRIDGE_OPTIONS.

Change-Id: Ifce7965040d96486ee8de2fba2ead9c54ee9a9f9
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76948
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-05 07:26:01 +00:00
Iru Cai 7e28c846c3 mb/hp: Add EliteBook 820 G2
Most of the components of this laptop are tested to work,
which is listed in the documentation.

Change-Id: Id8b3b7f735460c5e76a2dc9ab2d10154e6606ad6
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46630
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-08-04 21:45:53 +00:00
Elyes Haouas 9f59d2a906 coreboot-jenkins-node/Dockerfile: Upgrade lua5 from lua5.3 to lua5.4
Change-Id: Ic1450f0fa8eb69273aa907dea2eba8f7e7131ef1
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72510
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-08-04 20:55:45 +00:00
Tom Hiller daf6b8bc76 util/docker/coreboot-sdk: add mrc extraction packages
Add packages required to extract the `mrc.bin` from a ChromeOS firmware
image as per the instructions provided in
https://doc.coreboot.org/northbridge/intel/haswell/mrc.bin.html

Change-Id: I81ed4ef55f0ba745a8a0a0cc85c2b00360f59297
Signed-off-by: Tom Hiller <thrilleratplay@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67160
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-08-04 20:54:42 +00:00
Martin Roth f1ee2f7dc3 util/docker: refactor out and fix docker cache dir test
The test for the docker cache directory was used by two different
targets, so turn it into its own target.

Add missing $ for whoami commands.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ic5e1d28110097eb502959e81bafe77faa0fc7fae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76707
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-08-04 20:54:22 +00:00
Martin Roth 18fd3a2315 util/docker: Update coreboot-sdk-test to coreboot-jenkins-test
The coreboot-jenkins-test docker image takes the coreboot-jenkins-node
docker image and runs a series of tests to verify that things build
properly.

This was original created to test the coreboot-sdk, but build functions
like the documentation have been moved from the sdk image into the
jenkins node, so the test needs to be renamed.

Add the makefile target to the help and phony target list at the same
time.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I0e6282bbb163064f177c8e68e7180ba2bdc101f1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76706
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-08-04 20:53:47 +00:00
Nico Huber 799e79d166 bootsplash: Add ImageMagick voodoo
The JPEG decoder, that was added many years ago to display a boot-
splash in coreboot, has a few quirks. People used to do some voodoo
with GIMP to convert images to the right format, but we can also
achieve the same with ImageMagick's `convert`. The currently known
constraints are:
* The framebuffer's color format is ignored,
* only YCC 4:2:0 color sampling is supported, and
* width and height have to be a multiple of 16 pixels.

Beside that, we can only display the bootsplash if it completely
fits into the framebuffer. As the latter's size is often decided
at runtime, we can't do much more than offering an option to set
a specific size.

Change-Id: I564e0d89fb46503ff4c11e095726616700009968
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76564
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-08-04 20:53:24 +00:00
Fred Reitberger 3bcb7619b4 mb/amd/birman/port_descriptors_phoenix.c: Disable ASPM
Disable ASPM on ethernet, sd card, wwan, wlan, and ssd0 PCI devices.

This reduces kernel error logs such as:
[   15.172613] r8169 0000:01:00.0: PCIe Bus Error: severity=Corrected,
type=Data Link Layer, (Transmitter ID)

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I7b1605f18a91ed20bfc6ab70547c415e0278d290
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74970
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-04 20:53:05 +00:00
Karthikeyan Ramasubramanian 647abfd1d4 soc/amd/phoenix: Makefile change to include split hash table
Include multiple hash tables into relevant CBFS.

BUG=b:277292697
TEST=Ensure that all multiple hash tables are part of Myst BIOS image
with PSP verstage enabled.

Change-Id: I1601f4a01db5b2bbf8b5636ef9e69e41c1d9a980
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76589
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-04 20:52:36 +00:00
Karthikeyan Ramasubramanian 2c828436a7 soc/amd/phoenix: Add SVC call to inject v2 hash tables
On mainboards using Phoenix SoC with PSP verstage enabled, to
accommodate growing number of PSP binaries, multiple smaller hash tables
are introduced. Also some hash tables are in V2 format identifying the
concerned PSP binaries using UUID. Add SVC calls to support multiple
hash tables with different versions.

BUG=b:277292697
TEST=Build and boot to OS in Myst with PSP verstage enabled. Ensure that
all the hash tables are injected successfully. Ensure that PSP validated
all the signed PSP binaries using the injected hash tables successfully.

Change-Id: I64e1b1af55cb95067403e89da4fb31bec704cd4f
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76588
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-04 20:52:20 +00:00