Commit graph

225 commits

Author SHA1 Message Date
Nico Huber
ce642f08b9 Kconfig: Rework MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG
* Rename it to HAVE_VGA_TEXT_FRAMEBUFFER.
* Let drivers select it if they are in charge.
* Don't select it on the mainboard level if a driver handles it.

Change-Id: I2d9d09be9aa6d019e77460e69a245ad2d8cda4ea
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/19791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-02 18:35:41 +02:00
Arthur Heymans
000cc598cb mb/lenovo/*60: Remove not existing DIMMs from SPD map
Should result in a tiny speed bump in raminit since those addresses
are not checked for present DIMMs.

Checked in schematics of both Thinkpad X60 and T60 and tested to
configure raminit correctly for all DIMMs populated on X60.

Change-Id: I56c4f3176541bc75a8de3aac9f87526a77fc819b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-05-25 17:37:52 +02:00
Patrick Rudolph
c670a41ca7 mb/lenvovo/*: Clean mainboard.c and devicetree
* Move board specific SPI registers to devicetree
* Remove unused headers
* Remove obsolete methods
* Fix coding style
* Fix Thinkpad L520 SPI lvscc register

Except for Thinkpad L520, no functional change has been done,
just moving stuff around.

Change-Id: I692a5632030fe2fedbe9a90f86251000f1360fb2
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-05-21 16:38:52 +02:00
Nico Huber
a5fcc2e427 mb/lenovo/x60/t60: Remove fn_ctrl_swap option
The EC doesn't support it.

Change-Id: Id2964002406a5fcf992f0ffc3627e3f66a2bb13f
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/19654
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-05-11 16:44:46 +02:00
Arthur Heymans
c5fba2c17c nb/intel/i945: Define and use a default MMCONF_BASE_ADDRESS
Change-Id: I15550b1cc1a7ccfecba68a46ab2acaee820575b9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19648
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-05-11 16:39:35 +02:00
Patrick Rudolph
46cf5c29b3 nb/intel/i945: Move INTEL_EDID
All boards select INTEL_EDID, move it to nb folder.

Change-Id: I35f075a87f2d841856b208f9440cf41af6a3c8e6
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19086
Tested-by: build bot (Jenkins)
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-04-07 21:37:16 +02:00
Arthur Heymans
8e079000dc nb/i945/gma.c: Refactor panel setup
This reuses some of gm45 code to set up the panel.

Panel start and stop delays and pwm frequency can now be set in
devicetree.

Linux does not make the difference between 945gm and gm45
for panel delays, so it is safe to assume the semantics of those
registers are the same.

The core display clock is computed according to "Mobile Intel® 945
Express Chipset Family" Datasheet.

This selects Legacy backlight mode since most targets have some smm
code that rely on this.

This sets the same backlight frequency as vendor bios on Thinkpad X60
and T60.

A default of 180Hz is selected for the PWM frequency if it is not
defined in the devicetree, this might be annoying for displays that
are LED backlit, but is a safe value for CCFL backlit displays.

Change-Id: I1c47b68eecc19624ee534598c22da183bc89425d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18141
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-03-18 16:54:08 +01:00
Arthur Heymans
f77d6ba911 Select a default SeaBIOS PS2 timeout in H8 Kconfig
This timeout is probably needed on all devices with Lenovo H8 embedded
controllers so set the default there.

Change-Id: I830ab1894f7c0f10f55c82e398becf44d810852d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18274
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2017-02-28 14:49:15 +01:00
Francis Rowe
3054ca164e lenovo/x60: use correct BLC_PWM_CTL value
Bit 16 in BLC_PWM_CTL enables brightness controls, but the
current value is generic. Use the proper value, obtained
by reading BLC_PWM_CTL while running the VBIOS.

Change-Id: Ib273359e1c285b405a9bb26fc217c2f7e255b99f
Signed-off-by: Francis Rowe <info@gluglug.org.uk>
Reviewed-on: https://review.coreboot.org/10624
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-02-04 23:11:46 +01:00
Arthur Heymans
84e6881ba5 mb/lenovo/x60,t60: Move EC CMOS parameters in checksummed space
This allows for defaults to be applied to CMOS parameters
when cmos checksum is incorrect.

This probably results in changed cmos settings for current users of
these targets.

Change-Id: Ifec0093f4b0dbaa51b96812a041f0eaf5c58ee86
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17041
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2017-02-03 02:03:02 +01:00
Arthur Heymans
62902ca45d sb/ich7: Use common/gpio.h to set up GPIOs
This is more consistent with newer Intel targets.

This a static struct so it is initialized to 0 by default.
To make it more readable:
* only setting to GPIO mode is made explicit;
* only pins in GPIO mode are either set to input or output since this
  is ignored in native mode;
* only output pins are set high or low, since this is read-only on
  input;
* blink is only operational on output pins, non-blink is not set
  explicitly;
* invert is only operational on input pins, non-invert is not set
  explicitly.

Change-Id: I05f9c52dee78b7120b225982c040e3dcc8ee3e4e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17639
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-06 18:14:00 +01:00
Paul Menzel
7676730b9c mb/lenovo/x60: Remove PCI reset code from romstage
Commit bf264e94 (i945:) adds a PCI reset to the romstage, and commit
bc8613ec (Fix i945 based boards) fixes that to use the correct
delay of 200 ms. This code was then copied over, when adding support for
the Lenovo X60.

The reset was related to the shipped crypto card on the Roda RK886EX and
Kontron 986LCD-M, so is not needed on the Lenovo X60. So remove it.

TEST=Build and boot on Lenovo X60t.
Change-Id: Ia37d9f0ecf5655531616edb20b53757d5d47b42f
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/17703
Tested-by: build bot (Jenkins)
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-12-20 23:54:48 +01:00
Kyösti Mälkki
c86c6b33e8 intel cache-as-ram: Move DCACHE_RAM_BASE
Having same memory region set as both WRPROT and WRBACK
using MTRRs is undefined behaviour. This could happen if
we allow DCACHE_RAM_BASE to be located within CBFS in SPI
flash memory and XIP romstage is at the same location.

As SPI master by default decodes all of top 16MiB below
4GiB, initial cache-as-ram line fills may have actually
read from SPI flash even in the case DCACHE_RAM_BASE was
below the nominal 4GiB - ROM_SIZE.

There are no reasons to have this as board-specific setting.

Change-Id: I2cce80731ede2e7f78197d9b0c77c7e9957a81b5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17806
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-18 20:52:01 +01:00
Kyösti Mälkki
2c34e743a1 lenovo: Don't use extern with functions
Change-Id: I8313ba1d93922297e5061701dad47d07617d1dcd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17804
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-13 19:16:56 +01:00
Arthur Heymans
885c289bba nb/intel/i945: Make pci_mmio_size a devicetree parameter
Instead of hardcoding pci_mmio_size in the raminit code,
this makes it a parameter in the devicetree.

A safe minimum of 768M is also defined since using anything
less causes problems (if 4G of ram is used).

Change-Id: If004c861464162d5dbbc61836a3a205d1619dfd5
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/16856
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-12-11 14:17:06 +01:00
Kyösti Mälkki
8183025be9 intel/i945: Use romstage_handoff for S3
Don't use scratchpad registers when we have romstage_handoff
to pass S3 resume flag. Scratchpad register was read too
late in ramstage so acpi_is_wakeup_s3() did not evaluate
correctly.

This fixes low memory corruption at 0x1000-0x102c and the lack
of coreboot tables (util/cbmem not working) after S3 resume.

This also fixes console log from reporting early in ramstage
"Normal boot" while on "S3 resume" path.

Change-Id: I2922a15a90d2f8272c3482579bdd96f8f33e9705
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17675
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-11 08:58:07 +01:00
Arthur Heymans
1190e9cf42 x60,t60: do not add etc/ps2-keyboard-spinup for non-seabios payloads
Regardless of the payload chosen a file etc/ps2-keyboard-spinup
is added to cbfs. With this fix this file is only added to cbfs when
seabios is choses as a payload.

Change-Id: I37cf4c998856db2d297356776752643dba46a8f8
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/16146
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2016-10-13 14:59:16 +02:00
Arthur Heymans
e1f0ac4baa lenovo/x60: CST table: use MWAIT requests instead of P_LVLx I/O reads
Requesting low power acpi cpu c-states has two software interfaces:
Using P_LVLx I/O reads or using equivalent MWAIT requests.
This change makes it more consistent with newer targets that use MWAIT
requests.

There also exists extended intel acpi c-states which can be enabled
in two ways:
- using a substate hint to the mwait request (defined in bios);
- setting a model specific register (msr)

Currently this is done by setting the right msr bits but with this
change one can experiment by adding substate hints.

Change-Id: I9eeb5b008e2ddc2193725667f2c13582a4877e3c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/14801
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-11 23:34:18 +02:00
Elyes HAOUAS
8da96e57c8 mainboard/*/*/mptable.c: Improve code formatting
Change-Id: I341293cd334d6d465636db7e81400230d61bc693
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16723
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-26 13:32:21 +02:00
Elyes HAOUAS
f4df9d1156 mainboard/*/*/irq_tables.c: Use tabs for indents
Change-Id: Idc29373cb01f4304d22ae315812bd40f0aaa94c9
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16729
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-26 13:22:39 +02:00
Antonello Dettori
4bf48e8c33 lenovo/x60: transition away from device_t
Replace the use of the old device_t definition inside
mainboard/lenovo/x60.

The patch has been tested both with the arch/io.h definition of device_t
enabled and disabled in order to ensure compatibility while the
transaction takes place.

Change-Id: Icaceeae2fc7276efa82d37582ecac93aaf37c41c
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16372
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-02 18:10:10 +02:00
Arthur Heymans
874a8f961f i945: Enable changing VRAM size
On i945 the vram size is the default 8mb. It is also possible
to set it 1mb or 0mb hardcoding the GGC register in early_init.c

The intel documentation on i945, "Mobile Intel® 945 Express Chipset
Family datasheet june 2008" only documents those three options.
They are set using 3 bits. The documententation also makes mention
of 4mb, 16mb, 32mb, 48mb, 64mb but not how to set it.

The other non documented (straight forward) bit combinations allow
to change the VRAM size to those other states.

What this patch does is:
- add those undocumented registers with their respective vram size to
the i945 NB code;
- make this a cmos option on targets that have this northbridge.

TEST: build, flash to target, set cmos as desired and boot linux.
On Debian it can be found using "dmesg | grep stolen".
NOTE: dmesg message about reserved vram are quite different depending
on linux version

Change-Id: Ia71367ae3efb51bd64affd728407b8386e74594f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/14819
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-31 20:01:05 +02:00
Nico Huber
d23ee5de22 mainboard: Clean up boot_option/reboot_bits in cmos.layout
Since commit 3bfd7cc (drivers/pc80: Rework normal / fallback selector
code) the reboot counter stored in `reboot_bits` isn't reset on a reboot
with `boot_option = 1` any more. Hence, with SKIP_MAX_REBOOT_CNT_CLEAR
enabled, later stages (e.g. payload, OS) have to clear the counter too,
when they want to switch to normal boot. So change the bits to (h)ex
instead of (r)eserved.

To clarify their meaning, rename `reboot_bits` to `reboot_counter`. Also
remove all occurences of the obsolete `last_boot` bit that have sneaked
in again since 24391321 (mainboard: Remove last_boot NVRAM option).

Change-Id: Ib3fc38115ce951b75374e0d1347798b23db7243c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/16157
Tested-by: build bot (Jenkins)
Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com>
Reviewed-by: York Yang <york.yang@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-17 00:27:42 +02:00
Elyes HAOUAS
8ab989e315 src/mainboard: Capitalize ROM, RAM, CPU and APIC
Change-Id: Ia1f24d328a065a54975adde067df36c5751bff2d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/15987
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-14 19:06:25 +02:00
Alexander Couzens
6e1884ff5d lenovo/x60: add info message if dock is present
Change-Id: I5a6d41f815f65719780499fa18c131311a9dc8f7
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/16136
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-08-11 20:52:35 +02:00
Antonello Dettori
d6f7fd5261 lenovo/x60: add GPIOs initialisation before dock check
Add GPIOs initialisation before dock check.

Needed in order to properly detect the presence or absence of the lenovo
dock.
Previously the check always reported the dock as connected and currently
it always reports it as disconnected since the GPIOs are not properly
initialised during the check.

Tested and confirmed working.

Change-Id: I7fbf8c2262a1eb5dee9cbe5e23bf44f7f8181009
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16139
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-08-11 20:51:18 +02:00
Patrick Georgi
b9eee8e468 lenovo/x60: Fetch 16 bits when trying to parse bit 13
I'm not sure if that's the right fix here, but assuming the bit mask is
right, the inb is wrong.

Change-Id: I7e33019af088780a09be12513200bec63734bf97
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Found-by: Coverity Scan #1229556
Reviewed-on: https://review.coreboot.org/16026
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2016-08-03 22:53:21 +02:00
Kyösti Mälkki
15fa992cc8 intel/model_6ex: Prepare for dynamic CONFIG_RAMTOP
Change-Id: I9bfaa53f8d09962d36df1e86a0edcf100bb08403
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15229
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-21 00:49:12 +02:00
Arthur Heymans
7d38fafd96 lenovo/x60: add hda_verb.c
This creates a config for the x60 audio based
on values taken from vendor bios.

The pin config is stored in (for linux 4.5 at least):
/sys/class/sound/card0/hw*/init_pin_configs
In the left column there is the pin number.
In the right column there is the default configuration of that pin.
(This has to be done while running the proprietary bios)

More information on the sound card can be found in:
/proc/asound/card0/codec#*
This also hold the information of /sys/class/sound/

What is improved:
- internal microphone is chosen by default
- when jack is inserted it is chosen instead of internal speaker

Before this had to be done manually in alsa or pulseaudio.

TEST= check if internal microphone is used by default in
pavucontrol if you are using pulseaudio.
Plug in a jack with headphones and check if there
is sound output through these and not the build-in
speaker.

Change-Id: Id3b700fd84905a72cc1f69e7d8bfa6145f231756
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/15063
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-08 14:10:32 +02:00
Vladimir Serbinenko
b27c24f69b Workaround for unused variable warning.
Change-Id: I0a0c925509027f98f724d0a4347146f21ac06c02
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13624
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-09 19:58:14 +01:00
Alexander Couzens
f8970f53ef mainboard/lenovo: reserve century byte
The century byte is used by most RTC (default 0x32@nvram).
Even the century byte can disabled via ACPI it's more safe to reserve
it's space. Because some RTC will act with that byte anyhow.
Some OS overwrite it when syncronize the RTC.

Change-Id: I078c0c57215ccb925afa85b9d067f15268801ec9
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/11853
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-01-14 17:58:29 +01:00
Martin Roth
21dbc2fc3c ec/lenovo/h8: Fix IASL warnings
If any path in a method returns a value, IASL expects that all paths
within that method will return a value.

Presumably the MKHP method wouldn't get called unless there were a
pending event, but if no event is found, return a zero.

Fixes IASL warning:
dsdt.aml 1785: Method (MHKP, 0, NotSerialized)
Warning 3115 -           ^ Not all control paths return a value (MHKP)

This was the only IASL warning in most lenovo mainboards.

Change-Id: Id93dcc4a74bd4c18b78f1dde821e7ba0f3444da3
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12517
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-24 22:34:34 +01:00
Martin Roth
77c67b3d30 IASL: Enable warnings as errors
We've actually got more warnings now than when I first tested IASL
warnings as errors.  Because of this, I'm adding it with the option
to have it disabled, in hopes that things won't get any worse as we
work on fixing the IASL warnings that are currently in the codebase.

- Enable IASL warnings as errors
- Disable warnings as errors in mainboards that currently have warnings.
- Print a really obnoxious message on those platforms when they build.
***** WARNING: IASL warnings as errors is disabled!  *****
*****          Please fix the ASL for this platform. *****

Change-Id: If0da0ac709bd8c0e8e2dbd3a498fe6ecb5500a81
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10663
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-23 18:48:58 +01:00
Vladimir Serbinenko
d5d94ea90a intel/i945: Consolidate MADT handling
Change-Id: Ic3cdfa6086a45aa231aa817d5ef6998823589818
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7108
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-05 23:31:49 +01:00
Timothy Pearson
24391321e8 mainboard: Remove last_boot NVRAM option
The last_boot NVRAM option was deprecated and removed in
commit 3bfd7cc6.  Remove the last_boot option from all
affected mainboards to eliminate user confusion.

Change-Id: I7e201b9cf21dfe5dda156785bad078524098626d
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12316
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins)
2015-11-05 02:21:52 +01:00
Patrick Georgi
a73b93157f tree: drop last paragraph of GPL copyright header
It encourages users from writing to the FSF without giving an address.
Linux also prefers to drop that and their checkpatch.pl (that we
imported) looks out for that.

This is the result of util/scripts/no-fsf-addresses.sh with no further
editing.

Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/11888
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-31 21:37:39 +01:00
Paul Menzel
8fc5c64403 southbridge/intel: Move i82801gx/acpi/platform.asl to common/acpi
Commit 24813c14 (i945: Consolidate acpi/platform.asl) creates the file
in the directory `src/southbridge/intel/i82801gx/acpi`. Devices with the
southbridge `intel/i82801ix`, like the laptop Lenovo X200, use the exact
same ASL code though. So share this in the directory
`src/southbridge/intel/common/acpi`.

Change-Id: I33b7993bcdbef7233ed85a683b2858ac72c1d642
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/11881
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-23 22:29:01 +02:00
Paul Menzel
469f593498 cpu/intel: Move Power notification ASL code into common/acpi
Commit 24813c14 (i945: Consolidate acpi/platform.asl) creates the file
in the directory `src/cpu/intel/model_6dx/acpi`, although the devices
can also use different Intel CPU models like, for example,
`intel/model_6ex` on the Lenovo T60.

Therefore move the file to the directory `src/cpu/intel/common/acpi` so
that other devices, like Intel GM45 based devices, can also include it.

Change-Id: I90126b66a4d70468923622a8e3aebadeafcbf96f
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/11880
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-23 22:28:12 +02:00
Vladimir Serbinenko
551cff08d5 Derive lvds_dual_channel from EDID timings.
Based on the info by Felix Held.

Change-Id: Iab84dd8a0e3c942da20a6e21db5510e4ad16cadd
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/11857
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2015-10-11 10:07:12 +00:00
Aaron Durbin
9796f60c62 coreboot: move TS_END_ROMSTAGE to one spot
While the romstage code flow is not consistent across all
mainboards/chipsets there is only one way of running ramstage
from romstage -- run_ramstage(). Move the
timestamp_add_now(TS_END_ROMSTAGE) to be within run_ramstage().

BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built and booted glados. TS_END_ROMSTAGE still present in
     timestamp table.

Change-Id: I4b584e274ce2107e83ca6425491fdc71a138e82c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11700
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-24 16:12:44 +00:00
Francis Rowe
86da2c70e2 lenovo/x60: Enable VESA framebuffer mode (native graphics)
At present, no option exists for "Keep VESA framebuffer", which
means that text-mode will be used. Add the appropriate Kconfig
option.

Change-Id: Iaed07eba6d9288c857f7e7a0b0be1107071e49e5
Signed-off-by: Francis Rowe <info@gluglug.org.uk>
Reviewed-on: http://review.coreboot.org/10553
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <gaumless@gmail.com>
2015-06-22 19:23:22 +02:00
Francis Rowe
27ce9b1f27 lenovo/x60: Enable brightness controls (native graphics)
On i945 legacy brightness control is enabled by a single
bit in BLC_PWM_CTL. It's bit 16 or bit 0 (the other one
reverses polarity). Set the bit to enable brightness
controls.

Change-Id: Id855c4e91fe71fb489739e62fbe99ca22841acd2
Signed-off-by: Francis Rowe <info@gluglug.org.uk>
Reviewed-on: http://review.coreboot.org/7048
Reviewed-by: Martin Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-06-22 19:23:11 +02:00
Alexander Couzens
5eea458822 device_ops: add device_t argument to acpi_fill_ssdt_generator
`device_t device` is missing as argument. Every device_op function
should have a `device_t device` argument.

Change-Id: I7fca8c3fa15c1be672e50e4422d7ac8e4aaa1e36
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: http://review.coreboot.org/9598
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-05 21:11:43 +02:00
Vladimir Serbinenko
dd2bc3f819 igd.asl rewrite
Old igd.asl had inconsistent addresses (between _DOD and actual device)
and ghost devices. Any of those is enough to make brightness on windows
fail and make igd.asl out-of-ACPI-spec. Also old code favoured ridiculous
copying of the same thing 6 times per chipset. Leave only hooking up and
chipset-specific part in chipset directory. Move NVS handling and ACPI-spec
parts to a common file.

Change-Id: I556769e5e28b83e7465e3db689e26c8c0ab44757
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7472
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-05-28 08:27:10 +02:00
Patrick Georgi
b890a1228d Remove address from GPLv2 headers
As per discussion with lawyers[tm], it's not a good idea to
shorten the license header too much - not for legal reasons
but because there are tools that look for them, and giving
them a standard pattern simplifies things.

However, we got confirmation that we don't have to update
every file ever added to coreboot whenever the FSF gets a
new lease, but can drop the address instead.

util/kconfig is excluded because that's imported code that
we may want to synchronize every now and then.

$ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, *MA[, ]*02110-1301[, ]*USA:Foundation, Inc.:" {} +
$ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA:Foundation, Inc.:" {} +
$ find * -type f -exec sed -i "s:Foundation, Inc., 59 Temple Place[-, ]*Suite 330, Boston, MA *02111-1307[, ]*USA:Foundation, Inc.:" {} +
$ find * -type f -exec sed -i "s:Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.:Foundation, Inc.:" {} +
$ find * -type f
	-a \! -name \*.patch \
	-a \! -name \*_shipped \
	-a \! -name LICENSE_GPL \
	-a \! -name LGPL.txt \
	-a \! -name COPYING \
	-a \! -name DISCLAIMER \
	-exec sed -i "/Foundation, Inc./ N;s:Foundation, Inc.* USA\.* *:Foundation, Inc. :;s:Foundation, Inc. $:Foundation, Inc.:" {} +

Change-Id: Icc968a5a5f3a5df8d32b940f9cdb35350654bef9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/9233
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2015-05-21 20:50:25 +02:00
Vladimir Serbinenko
537283ddc5 lenovo: Remerge smbios_mainboard_bios_version.
Change-Id: I8df5b7f6707957b925f7bb4dc06a717252c70868
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10275
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Tested-by: build bot (Jenkins)
2015-05-21 10:34:38 +02:00
Vladimir Serbinenko
5e597572ef acpi: make fill_slit and fill_srat into arguments.
SLIT and SRAT are created this way only on amdk8 and amdfam10.
This saves the need of having a lot of dummies.

Change-Id: I76d042702209cd6d11ee78ac22cf9fe9d30d0ca5
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7052
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-20 19:51:40 +02:00
Vladimir Serbinenko
a5dc9f1be8 Remove useless extern gnvs declaration in smi handlers.
Change-Id: I3047badea8d4f61155f4e4f7d3d078426948162a
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10228
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-19 16:22:24 +02:00
Vladimir Serbinenko
cbcf28fef0 lenovo: Disable radio when suspending or turning off.
Without this some radios may remain operational. They may consume power but
the immediate demonstrable effect is wireless LED still being on.
Coreboot will reenable radios on resume or poweron.

Change-Id: I9fcb08880964b1594f779a246840bc3013a44afe
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10190
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-05-14 15:08:52 +02:00
Kyösti Mälkki
b85a87b7d6 intel SMI handlers: Refactor GPI SMI/SCI routing
Move the GPI interrupt routing selection between SMI/SCI from
mainboards to southbridge. There is speculation if this is all
just legacy APM stuff that could be removed with a followup.

Change-Id: Iab14cf347584513793f417febc47f0559e17f5a5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-on: http://review.coreboot.org/7967
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2015-04-28 07:59:13 +02:00