Commit Graph

458 Commits

Author SHA1 Message Date
Elyes HAOUAS 30201d4ab3 Makefile.inc: Remove redundant warning flag
'-Wstrict-aliasing' is turned on by '-Wall'.
'-Wstrict-aliasing' is only active when -fstrict-aliasing is active, so add it.

'BUILD_TIMELESS=1' on gigabyte/ga-945gcm-s2l  gives the same binary.

Change-Id: I51eb8241389f13d2659aef0a3b4b376ce9c651cf
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44216
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-17 07:08:31 +00:00
Angel Pons 464519769b assert.h: Do not use __FILE__ nor __LINE__ on timeless builds
When refactoring, one can move code around quite a bit while preserving
reproducibility, unless there is an assert-style macro somewhere... As
these macros use __FILE__ and __LINE__, just moving them is enough to
change the resulting binary, making timeless builds rather useless.

To improve reproducibility, do not use __FILE__ nor __LINE__ inside the
assert-style macros. Instead, use hardcoded values. Plus, mention that
timeless builds lack such information in place of the file name, so that
grepping for the printed string directs one towards this commit. And for
the immutable line number, we can use 404: line number not found :-)

Change-Id: Id42d7121b6864759c042f8e4e438ee77a8ac0b41
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42196
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-07-24 23:23:54 +00:00
Julius Werner bc1cb38ce1 Add qc_blobs repository
This patch adds a separate blobs repository for Qualcomm blobs,
analogous to the existing AMD blobs. Qualcomm's binary licenses allow
files to be redistributed and used by anyone, but they explicitly
require the user to agree to the license terms when just *downloading*
the binary (even if they're not using them to build any firmware). Some
community members do not like to have to agree to licenses for files
they're not actually using, so we are keeping these files separate from
the main blobs repository and adding an extra Kconfig to make sure the
user is aware of and must explicitly agree to this before downloading
these files.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I247746c1b633343064c9f32ef1556000475d6c4a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-06-30 08:57:03 +00:00
Angel Pons 104c3e5f9b Makefile.inc: Simplify fsp submodule check
TEST=Building Asrock H110M using FSP from repo updates the submodule.

Change-Id: I25023af88d878353a04db456009249da67e41521
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42778
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-06-28 21:45:47 +00:00
Martin Roth cfc170b213 src/*: Update makefiles to exclude x86 code from psp-verstage
The assumption up to this point was that if the system had an x86
processor, verstage would be running on the x86 processor.  With running
verstage on the PSP, that assumption no longer holds true, so exclude
pieces of code that cause problems for verstage on the PSP.

This change will add these files to verstage only if the verstage
architecture is X86 - either 32 or 64 bit.

BUG=b:158124527
TEST=Build and boot on Trembyle

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I797b67394825172bd44ad1ee693a0c509289486b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42062
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Eric Peers <epeers@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-23 21:28:40 +00:00
Kyösti Mälkki 44ef38f703 arch/x86: Remove NO_FIXED_XIP_ROM_SIZE
The variable SETUP_XIP_CACHE provides us a working
alternative.

Change-Id: I6e3befedbbc7967b71409640dc81a0c2a9b3e511
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41821
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-06-15 18:35:52 +00:00
Kyösti Mälkki 49c44cdccb arch/x86: Remove XIP_ROM_SIZE
When adding XIP stages on x86, the -P parameter was used to
pass a page size that covers the entire file to add. The same
can now be achieved with --pow2page and we no longer need to
define a static Konfig for the purpose.

TEST: Build asus/p2b and lenovo/x60 with "--pow2page -v -v" and
inspect the generated make.log files. The effective pagesize is
reduced from 64kB to 16kB for asus/p2b giving more freedom
for the stage placement inside CBFS. Pagesize remained at 64kB
for lenovo/x60.

Change-Id: I5891fa2c2bb2d44077f745619162b143d083a6d1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41820
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Keith Hui <buurin@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-06-15 18:34:45 +00:00
Furquan Shaikh 46514c2b87 treewide: Add Kconfig variable MEMLAYOUT_LD_FILE
This change defines a Kconfig variable MEMLAYOUT_LD_FILE which allows
SoC/mainboard to provide a linker file for the platform. x86 already
provides a default memlayout.ld under src/arch/x86. With this new
Kconfig variable, it is possible for the SoC/mainboard code for x86 to
provide a custom linker file as well.

Makefile.inc is updated for all architectures to use this new Kconfig
variable instead of assuming memlayout.ld files under a certain
path. All non-x86 boards used memlayout.ld under mainboard
directory. However, a lot of these boards were simply including the
memlayout from SoC. So, this change also updates these mainboards and
SoCs to define the Kconfig as required.

BUG=b:155322763
TEST=Verified that abuild with --timeless option results in the same
coreboot.rom image for all boards.

Change-Id: I6a7f96643ed0519c93967ea2c3bcd881a5d6a4d6
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42292
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-13 06:49:23 +00:00
Raul E Rangel 2b76ee0179 Makefile: Add missing APCB_EDIT_TOOL variable
Apparently I missed adding this variable definition.

BUG=b:157140753
TEST=Build APCBs with clean tree :)

Fixes: cbaa835f21 ("soc/amd/picasso/Makefile: Use apcb_tool to generate APCBs from SPDs")
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ia9055ed3507996cbf78687a97599aab3b0b39d6f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41738
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-27 16:00:05 +00:00
Duncan Laurie 6107064d66 make: Add a target and dependency to parse the devicetree with sconfig
This change adds a target to the top level Makefile that allows
building sconfig and generating static.c/static.h without building
the rest of coreboot.

It also adds $(DEVICETREE_STATIC_C) to the c-deps for each stage so
the files are generated before the build runs.

Signed-off-by: Duncan Laurie <dlaurie@google.com>
Change-Id: I4320288422230d8913dfa7cc7b7512775a1a797b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41439
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-22 01:50:11 +00:00
Patrick Georgi 6b5bc77c9b treewide: Remove "this file is part of" lines
Stefan thinks they don't add value.

Command used:
sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool)

The exceptions are for:
 - crossgcc (patch file)
 - gcov (imported from gcc)
 - elf.h (imported from GNU's libc)
 - nvramtool (more complicated header)

The removed lines are:
-       fmt.Fprintln(f, "/* This file is part of the coreboot project. */")
-# This file is part of a set of unofficial pre-commit hooks available
-/* This file is part of coreboot */
-# This file is part of msrtool.
-/* This file is part of msrtool. */
- * This file is part of ncurses, designed to be appended after curses.h.in
-/* This file is part of pgtblgen. */
- * This file is part of the coreboot project.
- /* This file is part of the coreboot project. */
-#  This file is part of the coreboot project.
-# This file is part of the coreboot project.
-## This file is part of the coreboot project.
--- This file is part of the coreboot project.
-/* This file is part of the coreboot project */
-/* This file is part of the coreboot project. */
-;## This file is part of the coreboot project.
-# This file is part of the coreboot project. It originated in the
- * This file is part of the coreinfo project.
-## This file is part of the coreinfo project.
- * This file is part of the depthcharge project.
-/* This file is part of the depthcharge project. */
-/* This file is part of the ectool project. */
- * This file is part of the GNU C Library.
- * This file is part of the libpayload project.
-## This file is part of the libpayload project.
-/* This file is part of the Linux kernel. */
-## This file is part of the superiotool project.
-/* This file is part of the superiotool project */
-/* This file is part of uio_usbdebug */

Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11 17:11:40 +00:00
Patrick Georgi 2faeb11fcd treewide: more SPDX header work
Change-Id: Ib78c322730ec6dfa9dcaafa16e5741cd3d351b8d
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-05-09 21:20:15 +00:00
Furquan Shaikh 8e66b23b35 Makefile: Set FMAP size to 0x200 for non-x86 boards with default fmd
This change updates FMAP_FMAP_SIZE for non-x86 boards using default
fmd file to be 0x200 just like for x86 boards.

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I3f58696b26fbb5363d67bec4056653da83485776
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40374
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-04-20 06:07:08 +00:00
Furquan Shaikh 5e1326a7d6 Makefile: Simplify calculation of region base with default fmd files
When using default fmd files, base of the fmap region is currently
calculated based on the size and base of previous fmap regions. Since
the existence of any fmap region is dependent on the selection of
certain CONFIG_* parameters, these calculations get complicated. Every
time base is calculated for a region, there need to be checks to see
which of the previous regions really exist. As the regions in default
fmd file are increased, these calculations and the conditional checks
get even more complicated.

This change introduces a Makefile variable FMAP_CURRENT_BASE which is
updated every time a new region is allocated space. This allows using
the same steps for determining the base of any fmap region
irrespective of the state of previous regions.

The way the code is organized it should be possible in the future to
also add a macro to perform the same steps (in case that is possible).

TEST=Verified that coreboot image generated remains unchanged for x86
and ARM boards using the default fmd files.

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I2a109462928b6e8b7930bbcc1a1ba45fa85de6ac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40373
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-04-20 06:06:46 +00:00
Michał Żygowski 11278dbabe SeaBIOS: fix threaded hardware initialization during oprom execution
Since SeaBIOS rel-1.7.5 CONFIG_THREAD_OPTIONROMS is not present in its
config. The threaded hardware initialization during optionrom execution
is now controlled with a CBFS file. Add appropriate integer to CBFS when
threaded hardware initialization is selected in coreboot's Kconfig.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I9b5a532b609c6addf31ccdb6be03ff2e937ad326
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40345
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-16 09:03:59 +00:00
Nico Huber e680caa298 Makefile.inc: Don't run `ifittool` with CONFIG_UPDATE_IMAGE
The dependency for `ifittool` was missing in the CONFIG_UPDATE_IMAGE
case. Which led us to the question: Why run `ifittool` in this case?
The idea of CONFIG_UPDATE_IMAGE is to update everything _but_ the
bootblock.

Change-Id: I7fd3bd1b56f495b16beb1e1f4b35b8cfcf25b2ba
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39803
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-25 10:51:50 +00:00
Elyes HAOUAS 04e0712f46 Treewide: Add some gcc's warning options
Change-Id: I789c8906542c59477b0037d39e7aa4fb2dcf22c0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2020-03-11 14:36:24 +00:00
Elyes HAOUAS 2119d0ba43 treewide: Capitalize 'CMOS'
Change-Id: I1d36e554618498d70f33f6c425b0abc91d4fb952
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38928
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Peter Lemenkov <lemenkov@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-24 14:10:00 +00:00
Nico Huber 0f6f70c394 Makefile.inc: Adapt $(spc) definition
GNU Make 4.3 is more picky about the $(spc) definition. It seems, the
variable ends up empty. The old definition worked for nearly 8 years,
RIP.

Tested with GNU Make 4.2.1 and 4.3.

Change-Id: I7981e0066b550251ae4a98d7b50e83049fc5586a
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38790
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-12 21:20:12 +00:00
Nico Huber 1c08a9a9c4 Makefile.inc: Use `define` for cbfs-files-processor-defconfig
The body contains a `#` and GNU make 4.3 disagrees with earlier versions
if it should be treated as a comment. Turn it into a `define` which has
clearer semantics regarding comments (interpretation is supposed to be
deferred until the variable is expanded).

Change-Id: I589542abbd14082c3ecc4a2456ebd809fb6911ea
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38793
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-12 20:07:21 +00:00
Martin Roth 12e9c5ee86 Makefile.inc: Ignore _HID & _ADR conflicts in Broadwell & Lynxpoint
We haven't been able to update IASL in 8 months because of this
conflict.  Ignoring it doesn't make things any worse than they are now.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Iced2e55e9f2aa7a262a5c1ffeff32af78acfa35e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38810
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-02-11 07:49:38 +00:00
Jacob Garber 84c7d2dfea xcompile: Disable null pointer optimizations
According to the C standard, accessing the NULL pointer (memory at
address zero) is undefined behaviour, and so GCC is allowed to optimize
it out. Of course, accessing this memory location is sometimes
necessary, so this optimization can be disabled using
-fno-delete-null-pointer-checks. This is already done in coreboot, but
adding it to xcompile will also disable it for all the payloads. For
example, coreinfo compiled with LTO libpayload crashes when this flag
isn't set, presumably because the compiler is optimizing something out
that it shouldn't.

Change-Id: I4492277f02418ade3fe7a75304e8e0611f49ef36
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38289
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-03 16:46:00 +00:00
Julius Werner 98eeb96135 commonlib: Add commonlib/bsd
This patch creates a new commonlib/bsd subdirectory with a similar
purpose to the existing commonlib, with the difference that all files
under this subdirectory shall be licensed under the BSD-3-Clause license
(or compatible permissive license). The goal is to allow more code to be
shared with libpayload in the future.

Initially, I'm going to move a few files there that have already been
BSD-licensed in the existing commonlib. I am also exracting most
contents of the often-needed <commonlib/helpers.h> as long as they have
either been written by me (and are hereby relicensed) or have an
existing equivalent in BSD-licensed libpayload code. I am also
relicensing <commonlib/compression.h> (written by me) and
<commonlib/compiler.h> (same stuff exists in libpayload).

Finally, I am extracting the cb_err error code definitions from
<types.h> into a new BSD-licensed header so that future commonlib/bsd
code can build upon a common set of error values. I am making the
assumption here that the enum constants and the half-sentence fragments
of documentation next to them by themselves do not meet the threshold of
copyrightability.

Change-Id: I316cea70930f131e8e93d4218542ddb5ae4b63a2
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38420
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-01-28 06:36:13 +00:00
Patrick Rudolph a48e8f52d8 Make: Add supermicro/smcbiosinfo to tools
Build the smcbiosinfo tool with other tools.

Fixes possible race condition on jenkins.

Change-Id: I38f7ee2fdef2818ad685b3de53ad74f7da50600f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: ron minnich <rminnich@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-08 16:24:04 +00:00
Patrick Rudolph 9e877ec60d util/supermicro: Add and use new tool smcbiosinfo
The BMC and tools interacting with it depend on metadata placed inside
the ROM in order the flash the BIOS.

Add a new tool smcbiosinfo, integrate it into the build system, and
generate a 128byte metadata file called smcbiosinfo.bin on build.

You need to provide the BoardID for every SMC mainboard through a new
Kconfig symbol: SUPERMICRO_BOARDID

Some fields are unknown, but it's sufficient to flash it using SMC
vendor tools.

Tested on Supermicro X11SSH:
* Flashing using the WebUI works
* Flashing using SMCIPMITool works

No further validation is done on the firmware.

Change-Id: Id608c2ce78614b45a2fd0b26d97d666f02223998
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-06 10:56:09 +00:00
Elyes HAOUAS c2092569d5 Makefile: Remove romcc
Change-Id: I2fe7fa8b23da3b909adc2b8bce59304acfb5b807
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2019-12-27 08:59:59 +00:00
Kyösti Mälkki 75396f67aa Makefiles: Remove -D__PRE_RAM__
All cases of testing for __PRE_RAM__ have been converted
to equivalent ENV_xxx definitions from <rules.h>.

Change-Id: Ib6cd598f17109cc1072818cebe4791f7410c3428
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37075
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-11-22 06:27:21 +00:00
Julius Werner 63c444a69b Remove imgtec/pistachio SoC
After removing urara no board still uses this SoC, and there are no
plans to add any in the future (I'm not sure if the chip really exists
tbh...).

Change-Id: Ic4628fdfacc9fb19b6210394d96431fdb5f8e8f1
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36491
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-20 10:10:44 +00:00
Patrick Georgi 4100c2a6e3 build system: Add various compiler flags that enable warnings on UB
Some types of Undefined Behavior can be determined statically at compile
time and gcc now has a set of flags that make it emit warnings in that
case instead of doing the __builtin_trap() / optimize / UD2-opcode dance
that silently breaks the resulting binary.

BUG=chromium:958270
BRANCH=none
TEST=abuild passes (probably not)

Change-Id: I3aa5ca00c9838cc7517160069310a1ef85372027
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-11-18 19:19:24 +00:00
Wim Vervoorn 556cc26337 src: Ignore Redundant offset remarks in ASL code
IASL reports unnecessary/redundant use of offset operator. These
messages are only masking usefull messages.
Add -vw 2158 so this message isn't reported.

BUG=N/A
TEST=build

Change-Id: Ie8507d3b3cb6f2e75cb87cd3e4bcc4280df27f77
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36857
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-18 16:21:57 +00:00
Julius Werner cefe89ee79 lib/fmap: Add optional pre-RAM cache
This patch adds an optional pre-RAM cache for the FMAP which most
platforms should be able to use, complementing the recently added
post-RAM FMAP cache in CBMEM. vboot systems currently read the FMAP
about half a dozen times from flash in verstage, which will all be
coalesced into a single read with this patch. It will also help
future vboot improvements since when FMAP reads become "free" vboot
doesn't need to keep track of so much information separately.

In order to make sure we have a single, well-defined point where the new
cache is first initialized, eliminate the build-time hardcoding of the
CBFS section offsets, so that all CBFS accesses explicitly read the
FMAP.

Add FMAP_CACHEs to all platforms that can afford it (other than the
RISC-V things where I have no idea how they work), trying to take the
space from things that look like they were oversized anyway (pre-RAM
consoles and CBFS caches).

Change-Id: I2820436776ef620bdc4481b5cd4b6957764248ea
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Joel Kitching <kitching@google.com>
2019-11-14 03:30:11 +00:00
Patrick Rudolph b1ef725f39 cpu/qemu-x86: Add x86_64 bootblock support
Add support for x86_64 bootblock on qemu.

Introduce a new approach to long mode support. The previous patch set
generated page tables at runtime and placed them in heap. The new
approach places the page tables in memory mapped ROM.

Introduce a new tool called pgtblgen that creates x86 long mode compatible
page tables and writes those to a file. The file is included into the CBFS
and placed at a predefined offset.

Add assembly code to load the page tables, based on a Kconfig symbol and
enter long in bootblock.

The code can be easily ported to real hardware bootblock.

Tested on qemu q35.

Change-Id: Iec92c6cea464c97c18a0811e2e91bc22133ace42
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-11-04 11:58:58 +00:00
Marshall Dawson 20ce4007eb Makefile, Kconfig: Add AMD dependency for amd_blobs repo
Add a Kconfig option for indicating agreement to use the contents of
amd_blobs.  Users should only download the repo after implicitely
agreeing to AMD's License text.  No formal documented agreement
is required.

Update Makfile.inc, similar to other submodules, to initialize and
checkout the submodule once the Kconfig option is selected.

Change-Id: I4ae807659db16756453dc3db2c51848291c681b8
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36416
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-10-31 12:31:12 +00:00
Marshall Dawson 376357c107 Makefile.inc: Consolidate submodule comments
Reduce duplicated comments explaining that submodules' settings in
.gitmodules are update=none, and that --checkout is required.  This
prepares for another submodule, and makes adding a third set of
comments unnecessary.

Change-Id: I7721333a61122284ed9975ecd2adc3271a879728
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36440
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-10-30 21:42:53 +00:00
Arthur Heymans 5e5fd41fcf Makefile.inc: Add a class 'all' to link files in all stage except SMM
Change-Id: I955dd2dc22cb3cfc4fdf1198cfd32f56475f97c9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33198
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-30 08:26:54 +00:00
Patrick Rudolph d9c799c529 build: Mark bootblock files on x86 as IBB
* Add cbfsoption --ibb to mark files as IBB
* Will be used by "Legacy FIT TXT" boot

Change-Id: I83313f035e7fb7e1eb484b323862522e28cb73d4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31497
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-10-18 15:38:19 +00:00
Nico Huber 17e9bcb9b8 util/sconfig: Issue header for exposed PCI and PNP names
Let `sconfig` output a C header file with the symbol names that we
generate since 5e2a2cd5e7 (util/sconfig: Expose usable PCI and PNP
device names).

We add another command line argument for the path to the header
file. As the file is similar in nature to our `config.h` we simply
put it in $(obj)/ too.

Change-Id: I8f87288c82f2844b61eba6534797a42b978b47bb
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35488
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-10-05 02:43:23 +00:00
Martin Roth ad84062b0d Makefile: Create the build directory before bootblock.bin
This was causing a failure when building platforms with no bootblock
when building with make -jXX

Change-Id: Ic4cd4fe8ac82bd1e9ce114dbd53763538d125af3
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35531
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-09-24 10:36:24 +00:00
Raul E Rangel 4007d7f8c7 Makefile: Pass .xcompile into genbuild_h
I'm moving the .xcompile file into the $(obj) directory so we can leave
the source pristine. We need to pass the location of .xcompile into
genbuild_h.sh.

BUG=b:112267918
TEST=Ran genbuild_h with and without an .xcompile and verified it was
passed.

Change-Id: I8b3a75b478fad92a0b09246f0a00b0580f8c4aef
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34240
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-08-28 18:29:15 +00:00
Patrick Georgi 3807ecdc54 build system: add kconfig/toada to tools list
Without this, we're lacking a serialization point in abuild when doing
parallel builds. This manifests in parallel attempts to write the toada
binary, which fails.

Change-Id: Id6ebbb3750284225670608e4927d80c4eea96afb
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35107
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2019-08-27 05:40:22 +00:00
Jacob Garber 9cd53c56ed Makefile.inc, payloads: Enable -Wvla
Variable length arrays are dangerous, so let's make sure they don't
sneak back into coreboot or any of the payloads.

Change-Id: Idf2488cf0efab51c9569a3789ae953368b61880c
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33846
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-20 20:57:01 +00:00
Kyösti Mälkki a3cb61a55d Makefile: Support HAVE_BOOTBLOCK=n case
With HAVE_BOOTBLOCK=n build of bootblock-class is skipped.

Inserts an empty 64-byte bootblock-region to coreboot.rom file,
cbfstool will fill in the CBFS master header relative location
at the end.

Change-Id: Iaee9200f72f31175aca597865e3c74fc68bec8a6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34477
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-08-07 21:22:12 +00:00
Jacob Garber 6e66b4e820 Makefile.inc: Enable -Wimplicit-fallthrough
Change-Id: Ic81ed9eb2ed5255a221082326b81c375456a6499
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34300
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-19 09:58:05 +00:00
Marshall Dawson 30cf155168 util/cbfstool: Add AMD BIOS compression tool for PSP
Add a utility to generate a compressed BIOS image for AMD Family 17h.

If the input is an elf file, the utility extracts the program portion
for compression.  Otherwise the file is compressed as-is.

In modern AMD systems, the PSP brings up DRAM then uncompresses the
BIOS image into memory prior to x86 beginning execution.  The PSP
supports a zlib engine, and interprets the first 256 bytes as a
header, where offset 0x14 containing the uncompressed size.  For
further details, see AMD Platform Security Processor BIOS Architecture
Design Guide for AMD Family 17h Processors (NDA only, #55758).

BUG=b:127766506
TEST=Use with WIP Picasso

Change-Id: Id1c54e0a6dae9e4a0362c6635fe8b8aa48a369d8
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2019-07-03 21:28:43 +00:00
Patrick Rudolph 5e3b92a924 Makefile: Use ifittool to update FIT
Depend on ifittool and use it to update FIT instead cbfstool FIT code.

Move the TOPSWAP / microcode handling out of cbfstool and implement it
in the Makefile.

The new FIT looks like the old one and has been tested on Broadwell-DE.

The TOPSWAP / microcode code path needs test on real hardware.

Change-Id: I687469d62557f81e9d88398cfc93182164fdac95
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31495
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
2019-06-24 09:42:52 +00:00
Nico Huber 6d7564cdfe Move -Wlogical-op into xcompile
Clang doesn't know `-Wlogical-op`, so let's move it into xcompile where
we can easily distinguish between the two. However, this requires us to
split out `GCC_ADAFLAGS*` from `GCC_CFLAGS*`.

Change-Id: I6a50de0bc5372f61337f237383d32645ba86b0fd
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33579
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-21 08:44:49 +00:00
Arthur Heymans 917420f7e8 Makefile.inc: Update 3rdparty/intel-microcode on USE_BLOBS
Change-Id: I0caeff3ff5613a594a79441e849440ebdc9a9b87
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33553
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-06-18 10:43:10 +00:00
Elyes HAOUAS 8c03542f92 Makefile.inc: Add -Wlogical-op warning option
Change-Id: Ie0491817a3a69c9f8e6f0f0d3cb755c642819df9
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33385
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-15 17:21:58 +00:00
Subrata Banik b5962a934a Rampayload: Able to build coreboot without ramstage
This patch removes all possible dependencies in order to build platform
with CONFIG_RAMPAYLOAD enable(without ramstage).

A. Create coreboot separate stage kconfigs

This patch creates seperate stage configs as below
1. HAVE_BOOTBLOCK
2. HAVE_VERSTAGE
3. HAVE_ROMSTAGE
4. HAVE_POSTCAR
5. HAVE_RAMSTAGE

B. Also ensures below kconfigs are aligned with correct stage configs

1. COMPRESS_RAMSTAGE and RELOCATABLE_RAMSTAGE are now enable if
CONFIG_HAVE_RAMSTAGE is selected.
2. COMPRESS_BOOTBLOCK will enable if CONFIG_HAVE_BOOTBLOCK is set
3. COMPRESS_PRERAM_STAGES will enable if CONFIG_HAVE_VERSTAGE
|| CONFIG_HAVE_ROMSTAGE is selected.

C. Also fix compilation issue with !CONFIG_HAVE_RAMSTAGE

On x86 platform:
Case 1: ramstage do exist: CONFIG_HAVE_RAMSTAGE=1
>> rmodules_$(ARCH-ramstage-y) will evaluate as rmodules_x86_32

Case 2: ramstage doesn't exist: CONFIG_HAVE_RAMSTAGE=0
>> rmodules_$(ARCH-ramstage-y) will evaluate as rmodules_

This patch fixes Case 2 usecase where platform doesn't select
CONFIG_HAVE_RAMSTAGE.

Also add option to create sipi_vector.manual based on $(TARGET_STAGE)
variable.

$(TARGET_STAGE)=ramstage if user selects CONFIG_HAVE_RAMSTAGE
$(TARGET_STAGE)=postcar if user selects CONFIG_RAMPAYLOAD

Change-Id: I0f7e4174619016c5a54c28bedd52699df417a5b7
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33142
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-06-11 15:49:25 +00:00
Nico Huber 342d3180d7 Makefile.inc: Extend version string for timeless builds
With the version string "TIMELESS", binaries are slightly smaller than
for a regular build. This may lead to false positive build tests if the
space is limited (e.g. bootblock). So let's make the string a little
longer.

Change-Id: I3bbf6f71d5bcd74728a3fe39734312690901d0ec
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32986
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-29 20:09:24 +00:00