Commit Graph

53664 Commits

Author SHA1 Message Date
Elyes Haouas dc15867e3b src/drivers/vpd/vpd.c: Use C99 flexible arrays
Use C99 flexible arrays instead of older style of one-element or
zero-length arrays.
It allows the compiler to generate errors when the flexible array does
not occur at the end in the structure.

Change-Id: Iab55c57ee5cac60911c9fe4cee8d86a252bde372
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76839
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-01 12:42:10 +00:00
Elyes Haouas 928584c31d security/intel/stm/StmApi.h: Use C99 flexible arrays
Use C99 flexible arrays instead of older style of one-element or
zero-length arrays.
It allows the compiler to generate errors when the flexible array does
not occur at the end in the structure.

Change-Id: I3ab3538b276fee5ed135bb4e88d9ef2cd6a00bb9
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76843
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-01 12:41:50 +00:00
Elyes Haouas 16f08cfeaf security/tpm/tpm{1,2}_log_serialized.h: Use C99 flexible arrays
Use C99 flexible arrays instead of older style of one-element or
zero-length arrays.
It allows the compiler to generate errors when the flexible array does
not occur at the end in the structure.

Change-Id: I79e4b34fe682f5f21415cb93cf65394881173b34
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76842
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-01 12:41:14 +00:00
Elyes Haouas b66a5551d5 payloads/coreinfo: Use C99 flexible arrays
Use C99 flexible arrays instead of older style of one-element or
zero-length arrays.
It allows the compiler to generate errors when the flexible array does
not occur at the end in the structure.

Change-Id: I17811256b04a17539d3ed77f406892ae77e97515
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76848
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-01 12:40:59 +00:00
Elyes Haouas 3bb076e521 libpayload/drivers/cbmem_console: Use C99 flexible arrays
Use C99 flexible arrays instead of older style of one-element or
zero-length arrays.
It allows the compiler to generate errors when the flexible array does
not occur at the end in the structure.

Change-Id: I3fd3f068ff731e1d9fed7c38ba6815e1eed86450
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-08-01 12:40:07 +00:00
Elyes Haouas ae51ee8c95 commonlib/timestamp_serialized.h: Use C99 flexible arrays
Use C99 flexible arrays instead of older style of one-element or
zero-length arrays.
It allows the compiler to generate errors when the flexible array does
not occur at the end in the structure.

Change-Id: Ibd1e4bc96a2f5eea746328a09d123629c20b272c
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76847
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-08-01 12:37:07 +00:00
Elyes Haouas a434f48bbe payloads/libpayload/include/coreboot_tables: Use C99 flexible arrays
Use C99 flexible arrays instead of older style of one-element or
zero-length arrays.
It allows the compiler to generate errors when the flexible array does
not occur at the end in the structure.

Change-Id: Icf3da1b0a0666769ae7b5d5f641b85436b324b4c
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76851
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-01 12:35:34 +00:00
Zheng Bao 63c952a66c soc/amd/common: Redefine EFS_OFFSET
The EFS_OFFSET is the relative address to flash base. We can not
assume the flash size is 16M.

The change will affect only Gardenia and Pademelon whose flash size
are 8M.

Change-Id: Ia68032db05264c55d333deec588ad9690a4ed2c1
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76764
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-01 12:26:33 +00:00
Kapil Porwal 340023fd28 mb/google/rex/var/screebo: Enable RTD3 for SSD
Currently, S0iX test is failing because S0i2 susbstate is blocked.
Enable RTD3 for SSD to unblock S0i2.2 substate residency.

BUG=none
TEST=Screebo can enter into S0iX.

S0iX substate residency w/o this CL -
```
Substate   Residency
S0i2.0     0
S0i2.1     38451594
S0i2.2     0
```

S0iX substate residency w/ this CL -
```
Substate   Residency
S0i2.0     0
S0i2.1     12108
S0i2.2     33878424
```

Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I50ac730820b3f29c387dc73bd90f1392a8797e24
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76831
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-08-01 11:52:44 +00:00
Kapil Porwal d88039cbfe mb/google/rex/var/screebo: Restrict ASPM to L1 for SD controller
Restrict ASPM to L1 for SD controller to avoid AERs.

BUG=b:288830220
TEST=No PCIE AER on SD controller on Screebo.

w/o this CL -
```
~ # lspci -s 00:06.0 -vvv | grep -i aspm
  LnkCap: Port #9, Speed 16GT/s, Width x4, ASPM L0s L1, Exit Latency L0s <4us, L1 <64us
          ClockPM- Surprise- LLActRep+ BwNot+ ASPMOptComp+
  LnkCtl: ASPM L1 Enabled; RCB 64 bytes, Disabled- CommClk+
  L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substates+
  L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+

~ # lspci -s 02:00.0 -vvv | grep -i aspm
  LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s unlimited, L1 <64us
          ClockPM+ Surprise- LLActRep- BwNot- ASPMOptComp+
  LnkCtl: ASPM L0s L1 Enabled; RCB 64 bytes, Disabled- CommClk+
  L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substates+
  L1SubCtl1: PCI-PM_L1.2- PCI-PM_L1.1- ASPM_L1.2- ASPM_L1.1-

~ # dmesg | grep -i -e "pci.*error"
[    0.734597] pcieport 0000:00:06.1: AER: Corrected error received: 0000:02:00.0
[    0.734882] rtsx_pci 0000:02:00.0: PCIe Bus Error: severity=Corrected, type=Data Link Layer, (Transmitter ID)
[    0.735258] rtsx_pci 0000:02:00.0:   device [10ec:522a] error status/mask=00001000/00006000
[    0.736159] pcieport 0000:00:06.1: AER: Corrected error received: 0000:02:00.0
[    1.520903] pcieport 0000:00:06.1: AER: Corrected error received: 0000:02:00.0
[    1.531587] rtsx_pci 0000:02:00.0: PCIe Bus Error: severity=Corrected, type=Data Link Layer, (Transmitter ID)
[    1.548894] rtsx_pci 0000:02:00.0:   device [10ec:522a] error status/mask=00001000/00006000
[    1.567490] pcieport 0000:00:06.1: AER: Multiple Corrected error received: 0000:02:00.0
```

w/ this CL -
```
~ # lspci -s 00:06.0 -vvv | grep -i aspm
  LnkCap: Port #9, Speed 16GT/s, Width x4, ASPM L0s L1, Exit Latency L0s <4us, L1 <64us
          ClockPM- Surprise- LLActRep+ BwNot+ ASPMOptComp+
  LnkCtl: ASPM L1 Enabled; RCB 64 bytes, Disabled- CommClk+
  L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substates+
  L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+

~ # lspci -s 02:00.0 -vvv | grep -i aspm
  LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s unlimited, L1 <64us
          ClockPM+ Surprise- LLActRep- BwNot- ASPMOptComp+
  LnkCtl: ASPM L1 Enabled; RCB 64 bytes, Disabled- CommClk+
  L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substates+
  L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+

~ # dmesg | grep -i -e "pci.*error"

```

Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I05f02c46486be42286fe9bc4f4be17763bb12b79
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76829
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-01 11:52:23 +00:00
Dtrain Hsu b2e7fa515d mb/google/dedede/var/cret: Generate new SPD ID for new memory parts
Add new memory parts in the mem_parts_used.txt and generate the
SPD ID for the parts. The memory parts being added are:
1. H54G56CYRBX247
2. H9HCNNNCPMMLXR-NEE
3. MT53E1G32D2NP-046 WT:B
4. K4UBE3D4AB-MGCL
5. K4UBE3D4AA-MGCR

BUG=b:290811418
BRANCH=dedede
TEST=FW_NAME=cret emerge-dedede coreboot chromeos-bootimage

Change-Id: Ib7f23dc3604fe1869772d92c9d7b8cc32ed9bbb9
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75882
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-01 07:57:14 +00:00
Matt DeVillier 3a795e0b23 soc/amd/common/cpu: Add Kconfig to program the PSP_ADDR MSR
The PSP_ADDR_MSR is programmed into the BSP by FSP, but not always
propagated to the other cores/APs. Add a hook to run a function
which will read the MSR value from the BSP, and program it into the
APs, guarded by a Kconfig. SoCs which wish to utilize this feature
can select the Kconfig.

BUG=b:293571109
BRANCH=skyrim
TEST=tested with rest of patch train

Change-Id: I14af1a092965254979df404d8d7d9a28a15b44b8
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76808
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-07-31 18:37:50 +00:00
Subrata Banik 3bd83b27af mb/google/rex: Allow to show early splash screen using GFX PEIM
This patch chooses to show the early splash screen which is an
OEM feature. The current implementation is relying on the Intel
FSP GFX PEIM to perform the display initialization.

Having this feature allows the platform to show the user notification
with 500ms since boot compared to traditional scenarios where first
user notification is coming from kernel (typically ~3sec+ after cpu
reset). Eventually this feature will help to improve the user
experience while booting Intel SoC platform based chromeos devices.

BUG=b:284799726
TEST=Able to see the early splash screen on google/rex.

Change-Id: I399ddb6618e774302200e8a87629647ba070d080
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76361
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-31 14:39:40 +00:00
Matt DeVillier 58fd7f4acb mb/google/cyan: Disable unused devices in devicetree
These devices are not present/used on CYAN boards.

Change-Id: I012b49562c2b932822823537032e2265901ddc81
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76799
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-07-31 14:12:04 +00:00
Matt DeVillier ee615d67b3 ec/google/chromeec: Unhide ChromeEC PD ACPI device
Set the ACPI status (_STA) for the PD device enabled+visible, to allow
coolstar's Windows drivers for USB4/Thunderbolt to attach.

TEST=build/boot Win11 on google/drobit, install USB4/TB drivers, verify
USB4/TB ports are functional for PD and data at USB4 speeds.

Change-Id: I84a20cfaf7e077469f8361b3da3b031d9fd84134
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
2023-07-31 14:09:52 +00:00
Matt DeVillier 55f30fdb3e ec/google/chromeec: Unhide GOOG0004 ACPI device
Set the ACPI status (_STA) for the EC ACPI to enabled+visible, to allow
coolstar's Windows drivers for the EC and keyboard backlight to attach.

TEST=build/boot Win11 on google/samus, install EC/kblight drivers,
verify keyboard backlight control functional.

Change-Id: I3e9578f1ef18b3bebb93a9ae2ae4e27bc38f648d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76790
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-07-31 14:09:30 +00:00
Matt DeVillier e6220e7170 soc/intel/apl: Hide PMC/IPC ACPI device from Windows
No drivers are needed/available, so hide the device to prevent
an unknown device from showing under Device Manager.
Linux does not use the ACPI _STA so no effect there.

Change-Id: I02efb64a845edc6e4fc559e7e99a7825abf4c2aa
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74892
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-07-31 14:07:51 +00:00
Matt DeVillier 0503274c74 soc/intel/apl: program VMX per Kconfig setting
While FSP programs the VmxEnable UPD per CONFIG_ENABLE_VMX, it doesn't
set the lock bit, which prevents Windows from enabling virtualization
on devices which support it. Call set_vmx_and_lock() to ensure the
lock bit is properly set.

TEST=build/boot Win11 on google/ampton,reef; verify virtualization
enabled.

Change-Id: I54ea0adb0a6d10f2df18f604b1f1e5a7a145dfb3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76804
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-07-31 14:06:32 +00:00
Jakub Czapiga 8beaf0f7e4 mb/google/rex: Create Ovis4ES variant
Ovis4ES variant supports only ESx SoCs. Existing Ovis variant will
support QS SoCs.

BUG=b:293409364
TEST=util/abuild/abuild -p none -t google/rex -b ovis4es -x -a
TEST=util/abuild/abuild -p none -t google/rex -b ovis -x -a

Change-Id: Iacf5ef6d3dfee8838fe13e68b254a84e4a6cf200
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76789
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-31 14:04:29 +00:00
Subrata Banik edd996103f mb/google/rex/var/ovis: Simplify the USB-C port mapping
This patch changes the `EC CONx Mapping` to fix the hot-plug issue
where attaching a device to USB-C port C1 can affect the USB-C
display over port C2.

Note: `PMC MUX Mapping` remains unchanged to reflect the underlying
board design where the physical MUX has swapped between C1 and C2
USB-C port.

Before:

| PMC MUX Mapping  |  Port C0    |   Port C1   |   Port C2     |
+------------------+-------------+-------------+---------------+
|  USB2-Port       |     2       |      3      |      1        |
|  USB3-Port       |     0       |      2      |      1        |


| EC CONx Mapping  |  Port C0    |    Port C1  |   Port C2     |
+------------------+-------------+-------------+---------------+
|  USB2-Port       |     2       |      3      |      1        |
|  USB3-Port       |     0       |      2      |      1        |

Physical Mapping between EC and SoC as below:

  Port C0 - EC CON0 ----> PMC MUX CON0
  Port C1 - EC CON1 ----> PMC MUX CON2
  Port C2 - EC CON2 ----> PMC MUX CON1

After:

| PMC MUX Mapping  |  Port C0    |   Port C1   |   Port C2     |
+------------------+-------------+-------------+---------------+
|  USB2-Port       |     2       |      3      |      1        |
|  USB3-Port       |     0       |      2      |      1        |


| EC CONx Mapping  |  Port C0    |    Port C1  |   Port C2     |
+------------------+-------------+-------------+---------------+
|  USB2-Port       |     2       |      1      |      3        |
|  USB3-Port       |     0       |      1      |      2        |

Physical Mapping between EC and SoC as below:

  Port C0 - EC CON0 ----> PMC MUX CON0
  Port C1 - EC CON1 ----> PMC MUX CON1
  Port C2 - EC CON2 ----> PMC MUX CON2

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I59e2630bc0f93321cc4b734fcf3c4cf254882477
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76758
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-07-31 14:04:04 +00:00
Jeremy Soller fe49f36ca8 mb/system76/addw1: Disable SaOcSupport
Typically we set SaOcSupport to allow overclocking RAM, but addw2 saw a
high rate of errors when using the provided 3200 MHz DIMMs. Disable OC
so modules run at the standard 2933 MHz.

Change-Id: I469b9c73d2e6bfa0b3c9175bcc87584aeaa95f75
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67837
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-31 14:03:25 +00:00
Tim Crawford 58a498e257 mb/system76/adl: Reset Realtek codec before configuring
Perform a codec reset to match all other System76 boards.

This applies commit 705ebbea04 ("mb/system76: Reset Realtek codec
before configuring") to boards that were added later.

Change-Id: I618cc042f1803d07bfc067d1999e1c44ab4a1fa9
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76754
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-07-31 14:02:49 +00:00
Matt DeVillier 1c611726d4 mb/google/rambi: Remove touchscreen as ACPI wake device
Users report having the touchscreen as a wake device causes many
spurious wakeups due to proximity to the keyboard when the lid is
closed, so remove it as a wake source.

TEST=build/boot google/glimmer, observe no unintended wakeups when
the lid is closed.

Change-Id: Id16cabcd21afa0b373ecddd9eb3b0b8befb71576
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76794
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-31 14:02:23 +00:00
Matt DeVillier 889cb1ff81 payloads/edk2: Update default branch for MrChromebox repo to 2023-06
Update the default branch used for MrChromebox's edk2 fork from 2023-04
to 2023-06. This updated branch has been rebased on the latest upstream
stable tag (edk2-stable202305), and fixes issues booting on AMD Zen
platforms (Picasso and newer).

TEST=build/boot google boards link, panther, lulu,reef, ampton, akemi,
banshee, zork, frostflow with edk2 payload selected.

Change-Id: I4867d453514f2b00f66ffdad50e091e5b80afdcb
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-07-31 14:02:01 +00:00
Jeremy Soller c4731fa9ee soc/intel/alderlake: Allow channel 0 for DDR5 memory-down
This matches the change done for DDR4 in commit 8509c25eec
("soc/intel/alderlake: Allow channel 0 for memory-down").

Fixes detection of the on-board RAM (Samsung M425R1GB4BB0-CQKOD) on the
System76 Lemur Pro 12 (Clevo L140AU). The Clevo L140*U are the only
boards in the tree using mixed memory topology.

Change-Id: I395f898472a9a8f857fd6b0564b95c787b96080b
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75285
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-07-31 14:01:27 +00:00
Felix Held ee004de969 util/sconfig: rework help text printing
Drop the program name and split the printf call with multiple lines of
text into separate printk calls.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I43df1fd02ce0fdbb6b22e1d4eda45017811c48d8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76774
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-31 14:00:52 +00:00
Arthur Heymans 166de9997a util/sconfig: Don't hardcode PCI device domain
Use the domain number in static references to pci device so that

  device domain 0x20 on
          device pci 00.0 on end
  end

results in

  DEVTREE_CONST struct device *const __pci_32_00_0 = &dev_#something;

in static.c

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I7a98b2325ee08feb1a3d1d4b333f3f4e53934b00
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76466
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-07-31 14:00:34 +00:00
Matt DeVillier 7779a08c61 mb/google/eve: set ACPI subsystem ID
Set the ACPI SSID using Google's project campfire ID for EVE, to allow
coolstar's Windows drivers to identify the device (since it uses a
generic ACPI _HID). Custom drivers are necessary under Windows since
the touchpad firmware is not fully I2C-HID compliant.

TEST=build/boot Win11 on google/eve, verify touchpad fully functional.

Change-Id: I3b8d56ff01d4cca7ba5c02f1aaab1a7049607dbc
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76802
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
2023-07-31 14:00:04 +00:00
Matt DeVillier 2ca55f2c18 drivers/i2c/generic: Add option to set ACPI subsystem ID
Change-Id: I7c9c938bd20d36be8fdfb0d95bb58a7259650693
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76801
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-07-31 13:59:52 +00:00
Tim Crawford 64640d3416 mb/system76/adl: Re-enable SATA DevSlp
CB:73353 switched ADL boards from using S0ix to S3. DevSlp can be
reenabled now as it no longer breaks suspend.

Change-Id: I618696833b7ed02e49c35d06021b730be91d879e
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76753
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
2023-07-31 13:57:26 +00:00
Tim Crawford 64b4253a3e mb/system76/rpl: galp7: Remove PL4 value
System76 EC since system76/ec@99dfbeaec3 sets PL4 values through PECI
based on AC state for all boards. Remove the static PL4 value from
coreboot since it won't be used.

Change-Id: I2bc37f12aab11910b4fe029efcee891a93257529
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
2023-07-31 13:57:01 +00:00
Tim Crawford 79a372036b mb/system76: Leave TBT LSX0 as FSP configured
Do not reconfigured LSX0 so that the FSP values are used.

Change-Id: I76e2ab01a5e853e3c1ac78b471ea0aa87d703d52
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76751
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-31 13:56:43 +00:00
Shon Wang 27830d0ec3 mb/google/brya/var/vell: Disable PCH USB2 phy power gating
The patch disables PCH USB2 Phy power gating to prevent possible display
flicker issue for vell board. Please refer Intel doc#723158 for
more information.

BUG=b:293535284
TEST=build and boot vell

Change-Id: I8a4d633fbd362188aedef373e515c7bfe5c4327a
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76770
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-07-31 13:56:18 +00:00
Arthur Heymans 91f5da4776 util/amdfwtool: Add some PSP entries to both levels
Some SoC like Genoa require this.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I01ff792e8016b16f34bc69722469b63cae5a42ff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76468
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2023-07-31 13:55:49 +00:00
Matt DeVillier 6066807dd2 mb/google/link: Enable HP jack output under Windows
The EAPD pin needs to be enabled and set in order for the headphone
jack to work properly. It's already done for the speaker in the
beep verbs, but needs to be done for the HP jack as well in order
for output to work properly under Windows.

TEST=build/boot Win11 on LINK, verify headphone output functional
when headphones plugged in.

Change-Id: I411d7317aefc1154635c4c17ca0dc1e37c9f40f4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76746
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-31 13:55:15 +00:00
Raymond Chung 53e5874449 mb/google/brya: Create pirrha variant
Create the pirrha variant of the nissa reference board by copying
the template files to a new directory named for the variant.

(Auto-Generated by create_coreboot_variant.sh version 4.5.0).

BUG=b:292134655
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_PIRRHA

Change-Id: Idc0a4dbb467cbdb91a5ed55c5e0a9e898e775b11
Signed-off-by: Raymond Chung <raymondchung@ami.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76768
Reviewed-by: SH Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-31 13:54:53 +00:00
Yunlong Jia 11ba8ebbcc mb/google/nissa/var/gothrax: Adjust touchscreen driver
Vendor changes touchscreen firmware to use hid method instead of i2c.

BUG=b:274707912
BRANCH=None
TEST=emerge-nissa coreboot

Change-Id: I8e9e0b757e337db6af3fbf3cd4fdbc0079646179
Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76680
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2023-07-31 05:52:05 +00:00
Elyes Haouas 34fb5ab4e9 soc/intel/common/block/pcr: Remove useless break after a return
Change-Id: Ie7f2144d0af21ba111464dfd135159704a3d82b7
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76474
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-31 05:26:57 +00:00
Matt DeVillier 16b6937ea7 mb/google/{auron,link,slippy}/acpi: Drop EC serial port
The EC serial port on these devices is not accessible to the end user
and exposing it to the OS via ACPI serves no purpose. Debugging over
the EC serial port (via the servo interface) does not require the
ACPI exist. Drop it since it's not needed and serves no purpose.

TEST=build/boot Win11 on auron/link/slippy, verify Windows Device
Manager no longer shows an unusable COM port.

Change-Id: If453bfca8e094aa06043293bdf91a40c38cc7866
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76793
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-31 05:10:31 +00:00
Elyes Haouas 8bd2b5c657 Doc/releases/coreboot-4.21: Update toolchain section
Change-Id: Ie153212a6efa98d7a8942097a1d263837510074d
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-07-31 04:32:12 +00:00
Elyes Haouas b39abc7bab soc/intel/alderlake/hsphy.c: Use C99 flexible arrays
Use C99 flexible arrays instead of older style of one-element or
zero-length arrays.
It allows the compiler to generate errors when the flexible array does
not occur at the end in the structure.

Change-Id: Id0baf970dbe94a8ebf75f8dbabc6abe345d1c454
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76783
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-07-31 04:29:12 +00:00
Elyes Haouas f7926461da drivers/intel/fsp2_0/fsp_timestamp.c: Use C99 flexible arrays
Use C99 flexible arrays instead of older style of one-element or
zero-length arrays.
It allows the compiler to generate errors when the flexible array does
not occur at the end in the structure.

Change-Id: I03c21e180e9e399e5cb451bf3b9cfb6484cab68b
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76778
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-31 04:28:52 +00:00
Elyes Haouas 242bac0e16 commonlib/bsd/cbfs_serialized.h: Use C99 flexible arrays
Use C99 flexible arrays instead of older style of one-element or
zero-length arrays.
It allows the compiler to generate errors when the flexible array does
not occur at the end in the structure.

Change-Id: I00807a435a21e078c89f797cfd0b00d03604ea0e
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76786
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-31 04:28:31 +00:00
Elyes Haouas bfdb7551b1 Update arm-trusted-firmware submodule to upstream master
Updating from commit id c161772f4:
2023-06-08 15:47:09 +0200 - (Merge "refactor(el3-spmc): add emad_advance()" into integration)

to commit id 37366af8d:
2023-07-28 17:04:54 +0200 - (Merge "fix(cpus): fix minor issue seen with a9 cpu" into integration)

This brings in 287 new commits.

Change-Id: Ic364a54154a7b4c5757f9d8abafe2047159ea3ba
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76481
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-07-30 19:26:21 +00:00
Felix Held 0df754bdb0 soc/amd/common/data_fabric/domain: skip reserved resources for ACPI
The non-PCI resources added to the domain device are resource consumers,
so they mustn't be reported as resource producers. To make sure that
this is the case, skip all resources that have the IORESOURCE_RESERVE
flag set in amd_pci_domain_fill_ssdt.

Commit 7a5dd781d1 ("soc/amd/common/data_fabric/domain: provide
amd_pci_domain_fill_ssdt") that introduced amd_pci_domain_fill_ssdt
already contained the bug, but since no MMIO range consumers were added
back then, the bug only became visible when commit 32169720bb
("soc/amd/common/data_fabric/domain: report non-PCI MMIO resources")
added the reserved non-PCI MMIO resources to the domain device's
resources resulting in MMIO producer objects being generated for MMIO
consumers. Those producers that should have been consumers then
overlapped with the actual MMIO resource producers which caused Windows
to BSOD with an ACPI_BIOS_ERROR.

TEST=The non-PCI MMIO resources are no longer added as resource
producers and Windows boots again on google/frostflow.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: Matt DeVillier <matt.devillier@gmail.com>
Change-Id: Ib099675bc5bea93bf7c2a80f741bef067fd37a58
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76818
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-07-30 17:23:38 +00:00
Felix Held a239cf488a soc/amd/common/data_fabric/domain: continue after unassigned resource
When iterating over the resource list in amd_pci_domain_fill_ssdt, don't
return when a resource is unassigned, but just continue to the next loop
iteration so the resulting SSDT will be complete and not broken due to
a missing resource template footer and the scope not being closed.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I39fe516f27a6d971fb9c57a1e64ead79d23aff08
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76817
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-07-30 17:23:13 +00:00
Elyes Haouas d686ee24a7 drivers/intel/gma/intel_bios.h: Use C99 flexible arrays
Use C99 flexible arrays instead of older style of one-element or
zero-length arrays.
It allows the compiler to generate errors when the flexible array does
not occur at the end in the structure.

Change-Id: I80b4b2df4a38dcbb28d928018446e91acae90ee6
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76779
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-07-30 10:00:38 +00:00
Elyes Haouas 7465c16e73 lib/cbmem_console.c: Use C99 flexible arrays
Use C99 flexible arrays instead of older style of one-element or
zero-length arrays.
It allows the compiler to generate errors when the flexible array does
not occur at the end in the structure.

Change-Id: I3d716b29d8e28584a0c9e4056d4c93dca2873114
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76780
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-30 09:59:46 +00:00
Elyes Haouas a8a0d394dd sb/intel/lynxpoint/me: Use C99 flexible arrays
Use C99 flexible arrays instead of older style of one-element or
zero-length arrays.
It allows the compiler to generate errors when the flexible array does
not occur at the end in the structure.

Change-Id: If31cbc5ae184c4eb66011666c1bb655fa16afba0
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76781
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-07-30 09:59:33 +00:00
Elyes Haouas 3a48e52dfe include/commonlib/bsd/mem_chip_info.h: Use C99 flexible arrays
Use C99 flexible arrays instead of older style of one-element or
zero-length arrays.
It allows the compiler to generate errors when the flexible array does
not occur at the end in the structure.

Change-Id: Ia1d597c0e3e86db8c13829e58a8a27d9de1480b4
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76788
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-30 09:59:21 +00:00