Commit Graph

5919 Commits

Author SHA1 Message Date
Patrick Georgi c75c79bd02 mptable: Get rid of fixup_virtual_wire
As stated in some code files, fixup_virtual_wire was established
to avoid touching 200 invocations of the mptable code.

Let Coccinelle do it:
  @@
  type T;
  identifier v;
  @@
  -void fixup_virtual_wire(T v)
  -{ ... }

  @@
  expression A;
  identifier v;
  @@
  -v = smp_write_floating_table(A);
  +v = smp_write_floating_table(A, 0);

  @@
  expression A;
  identifier v;
  @@
  -v = smp_write_floating_table(A, 0);
  -fixup_virtual_wire(v);
  +v = smp_write_floating_table(A, 1);

Change-Id: Icad8a063380bf4726be7cebb414d13b574112b14
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/245
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-13 01:10:44 +02:00
Patrick Georgi 6eb7a53169 mptable: Refactor lintsrc generation
We copied pretty much the same code for generating mptable entries for
local interrupts (with some notable exceptions).
This change moves these lines into a generic function "mptable_lintsrc"
and makes use of it in many places.

The remaining uses of smp_write_lintsrc should be reviewed and replaced
by mptable_lintsrc calls where possible, and smp_write_lintsrc made static.

This patch was generated using Coccinelle:
  @@
  expression mc;
  expression isa_bus;
  @@
  -smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x0);
  -smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x1);
  +mptable_lintsrc(mc, isa_bus);

  @@
  expression mc;
  expression isa_bus;
  @@
  -smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, isa_bus, 0x0, MP_APIC_ALL, 0x0);
  -smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, isa_bus, 0x0, MP_APIC_ALL, 0x1);
  +mptable_lintsrc(mc, isa_bus);

  @m@
  identifier mc;
  expression BUS;
  @@
  -#define IO_LOCAL_INT(type, intr, apicid, pin) smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, BUS, (intr), (apicid), (pin));
  ...
  -IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
  -IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
  +mptable_lintsrc(mc, BUS);

Change-Id: I97421f820cd039f5fd753cb0da5c1cca68819bb4
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/244
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-13 01:10:31 +02:00
Rudolf Marek 3a1fe9dec1 Make Asus A8V-E SE better ACPI citizen.
Use the SSDT autogen infrastructure to support the automatic reserved resources,
automatic P-state generation and automatic _CRS PCI0 method.

Change-Id: Ic56a92eeb70a0a2a2d6de2507009ec3a832c83b3
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/251
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-13 01:09:50 +02:00
Christoph Grenz 8ae574c805 w83627hf: ASL include containing virtual device tree of the SuperIO
Add a ACPI Source Language snippet to superio/w83627hf which maps the
SuperIO and most of the logical devices to PnP devices, exposing
configuration options and chip power management to the OS.
Written using the Winbond W83627HF/F datasheet.

Change-Id: I1108d29b341ef78fe7f1e574f98b680aada39daf
Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de>
Reviewed-on: http://review.coreboot.org/223
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-12 07:56:29 +02:00
Christoph Grenz 80311eab8c amdk8: ASL include for K8 temperature sensor support in ACPI
Add a ACPI Source Language snippet which if included as
shown in the comments in the file, exposes the 4 possible
temperature sensors in the CPU as ACPI thermal zones.

Change-Id: I94dd773108e348a0fdb9d2f8d6cfe415d5fa0339
Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de>
Reviewed-on: http://review.coreboot.org/222
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-12 07:54:25 +02:00
Kerry Sheh 55437c57a9 SB800 RAID: add kconfig option RAID_MISC_ROM_POSITION
SB800 RAID ROM require to put the misc ROM to specific position,
this patch enable user to put the RAID misc ROM to the right place
in the coreboot image.

Change-Id: I4fc64df8e091fb0cccd063826ab31a4f198942d1
Signed-off-by: Kerry She <kerry.she@amd.com>
Signed-off-by: Kerry She <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/249
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-12 07:45:09 +02:00
Kerry Sheh 0e6344e1cf SB800: Sata Enable bus master and enable ahci for AHCI/RAID mode
In order to make sure AHCI/RAID ROM works correctly
For SB800_SATA_AHCI or SB800_SATA_RAID mode, SATA should
enable bus master and the ahci also should be enabled.

Change-Id: I9d9c557816d364d8373fe343860ad5fe45988200
Signed-off-by: Kerry She <kerry.she@amd.com>
Signed-off-by: Kerry She <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/248
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-12 07:43:48 +02:00
Kerry Sheh 56ed40acb2 avalue/eax-785e: Get SATA Mode from Kconfig option
Change-Id: I67aab3ba7de85337e2cf83b6d1be63cb04bf0fcd
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/233
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-12 03:42:51 +02:00
Kerry Sheh d7e856b9cb sb800: Add Kconfig option ENABLE_IDE_COMBINED_MODE
Add this option to enable/disable SATA IDE Combined Mode feature

Change-Id: I1ab8acd27947a71baf954f44d0741f81f48e5541
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/231
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-12 03:41:38 +02:00
Kerry Sheh 2c7c37a016 persimmon: complete the sb800 devicetree
sb800 cimx entry sb_Before_Pci_Init was called in the device 16.2
enable_dev() function. If the devicetree don't have this device,
then sb_Before_Pci_Init will not get called.
So the missing sb800 USB3 devicees was add to the mainboard devicetree.
Because of no physical usb connector connected to USB3, the USB3 device setting was off.

Change-Id: If060ccb43df7fbe88bafc61e9e600a9120575437
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/232
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-12 03:40:18 +02:00
Marc Jones 5f145faff8 Don't do a call as the first instruction in libpayload.
Doing a call before the payload has set up its stack is risky. The stack may
not be in a favorable location. Normally this is not an issue with coreboot
or other well behaved callers.

Change-Id: Ie6f6748a471324b29ebad045c807dfc9f4b92034
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/240
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-11 11:47:06 +02:00
Oskar Enoksson 07bf911931 Fixed broken MTRR for >4GB memory on AMD K8 fam 0fh rev <=E
AMD K8 rev F and later implements a bit SYSCFG_MSR_TOM2WB to
mark dram memory above 4GB as WB. However, AMD K8
rev E and earlier don't implement this bit and therefore need
MTRR spanning dram memory above 4GB. The current implementation
of amd_setup_mtrrs never generate MTRR above 4GB.
This caused memory > 4GB not to be recognized in e.g. Linux on those
rev E or older platforms. This commit should fix that bug.

Signed-off-by: Oskar Enoksson <enok@lysator.liu.se>
Change-Id: Ie568a52a8eb355969c86964d5afc4692e60f69c1
Reviewed-on: http://review.coreboot.org/238
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-11 08:49:59 +02:00
Kerry Sheh 75df1062a1 mainboard: complete the sb800 devicetree even device is off
sb800 cimx entry sb_Before_Pci_Init was called in the device 16.2
enable_dev() function. If the devicetree don't have this device,
then sb_Before_Pci_Init will not get called.

Change-Id: I76ebad842e90b0f740abbec031165d7c39a80abf
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/230
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-11 08:11:59 +02:00
Kerry Sheh 4e9c4c8cc2 sb800: sata combine mode configure fix
Using micro CIMX_OPTION_ENABLED/CIMX_OPTION_DISABLED to
configure SataIdeCombinedMode is wrong.

sbPowerOnInit() use SataIdeCombinedMode to determine whether hide the IDE controller
  0: IDE controller is exposed and Combined Mode is enabled.
     SATA controller has control over Port0 through Port3,
     IDE controller has control over Port4 and Port5
  1: IDE controller is hidden and Combined Mode is disabled,
     SATA controller has full control of all 6 Ports when operating in non-IDE mode

Change-Id: I32e7101737f1dbfff49daa58670e6820b476b250
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/229
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-11 08:07:21 +02:00
Kerry Sheh 1386fa747d persimmon: sb800 sata mode configure update
persimmon configure sb800 sata mode according to the
southbridge kconfig selection.

Change-Id: I44a9c36ca68b4a0e1086f04c4338d3a5f536fdca
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/227
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-11 07:59:43 +02:00
Kerry Sheh d4a0e7d0b6 sb800: Add sata ahci/raid mode kconfig option
If sb800 sata was configured as ahci or raid mode,
give the option to add ROM files.

Change-Id: I87a7814930ce3a7c38cde1e235d151223eea2107
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/225
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-11 07:59:12 +02:00
Kerry Sheh f8adf7a129 pci_ids: Add sb800 SATA device raid mode device id
sb800 SATA device have different device id with different configure
mode, 4392h for RAID mode, 4393h for RAID5 mode

Change-Id: If54f7751f531c94ee725309a2a5c255390935ead
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/226
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-03 23:27:22 +02:00
enok71 af90275a41 TINY_BOOTBLOCK problem-fix on amdk8+amd8111 platforms
The hp/dl145_g1 motherboard did not work since commit
1f7d3c5672 (svn 6124). That commit added
TINY_BOOTBLOCK for amd8111 southbridge. The result was that the boot process
stopped very early (no console output whatsoever). The same symptom was
reported on other AMDK8 based boards with amd8111 southbridge chips. This
commit seems to fix the bug. It adds a bootblock.c under
src/northbridge/amd/amdk8 that calls enumerate_ht_chains. Probably the
problem was that enum_ht_chains needs to be called before the southbridge
bootblock.c function, not after.

Change-Id: I74fb892aa39048e2d0e76c081b713f825d67f2d4
Signed-off-by: Oskar Enoksson <enok@lysator.liu.se>
Reviewed-on: http://review.coreboot.org/235
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-03 23:17:33 +02:00
QingPei Wang 8eb4273290 Add AMD Family 10h PH-E0 support
the patch file comes from
src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevE
/F10MicrocodePatch010000bf.c

Change-Id: If701c8a908edf1c486665d3ce4df65da0f65c802
Signed-off-by: QingPei Wang <wangqingpei@gmail.com>
Reviewed-on: http://review.coreboot.org/202
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2011-09-24 15:58:12 +02:00
Raymond Danks 62ff00e13f mkelfImage: Use -fno-stack-protector if supported by gcc
Gcc 4.1 comes with an SSP https://wiki.ubuntu.com/GccSsp
This is disabled to work around '__stack_chk_fail' symbol not found failures
http://www.coreboot.org/FAQ/Obsolete#How_do_I_fix_stack_chk_fail_errors.3F

The presence of -fno-stack-protector is tested for automatically by configure.

Change-Id: I28ef158829f5935f985cfd5a5440733685cf479a
Reported-by: Raymond Danks <raymonddanks@gmail.com>
Signed-off-by: Raymond Danks <raymonddanks@gmail.com>
Reviewed-on: http://review.coreboot.org/112
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2011-09-24 12:55:26 +02:00
Stefan Reinauer 03f82bd787 Use ACPI text fields consistently with all other boards
LXBIOS and LXB-DSDT are not used in other parts of the tree.
Make names consistent across the tree.

Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Change-Id: I91caeac09fd2401a36e53bd061d249b236a48e43
Reviewed-on: http://review.coreboot.org/224
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2011-09-21 00:31:45 +02:00
Marc Jones 8487229b91 Persimmon doesn't have HDMI so the GNB HD Audio should be disabled.
Change-Id: Ic960fe09fbed2c8a31c7c9ac2c54f6c88efebed3
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/219
Reviewed-by: Frank Vibrans III <frank.vibrans@amd.com>
Tested-by: build bot (Jenkins)
2011-09-17 20:28:19 +02:00
Marc Jones 96be74c7f6 Enable SATA AHCI for faster boot with SeaBIOS.
Change-Id: Ibd87422680350c112eabe1bb73b237031c3e9d6b
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/220
Tested-by: build bot (Jenkins)
Reviewed-by: Frank Vibrans III <frank.vibrans@amd.com>
2011-09-17 01:53:41 +02:00
efdesign98 d7a696d0f2 Persimmon updates for AMD F14 rev C0
These are the changes for the AMD Persimmon mainboard
required to support the update of the AMD Family 14
cpu to rev C0.  There are many warning fixes; the agesa-
wrapper.c file has been changed to fix the amdinitlate
and amdlaterunaptask routines, and more.

Change-Id: I6de43379a2819cea5169db5f21d4841f9a4942a7
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/137
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-09-16 01:51:00 +02:00
efdesign98 83d59b945c Build warning fix for AMD Family 12
This trivial change adds a prototype to an existing
header file to fix a build warning for the AMD family
12 cpus.

Change-Id: Ic666bfbef867d17607eaa0f59570aea987a31f93
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/218
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-09-15 19:55:35 +02:00
efdesign98 d91c9b7e3c AMD Inagua platform updates
These changes update the Inagua platform.  The changes
include modifying the Kconfig to suggest video bios
and ahci rom implementations, changing the dimm spd
code to use the correct bus addresses, cleaning up the
makefile a bit, and fixing a duplicate definition
warning associated with the BIOS_SIZE value.

Change-Id: Idab88dda48f08877dbbd2de3136bdf0e54e31247
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/136
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-09-15 19:23:56 +02:00
efdesign98 2c66060169 AMD Torpedo platform updates
This update fixes warnings and supports as necessary
the Agesa infrastructure changes required to support
the AMD Family 14 cpu update to rev C0.

Change-Id: Ib08b49695b925b81f796bf299141fe6f845fdef8
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/138
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-09-15 17:30:07 +02:00
efdesign98 4d2d5d5b3e AMD Agesa macro expansion fix
This change fixes the use of a macro that was
previously modified to fix a warning.  The macro
was used in a manner that doubly incremented a
pointer.  The pointer increment was removed from
the macro call and moved elsewhere.  In addition,
an unused macro was removed from both Family 12
and Family 14 code.

Change-Id: I577794bbc55d18f21170dda1d0bbdc6d776ce392
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/217
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-09-15 09:56:08 +02:00
efdesign98 3c59158810 AMD SB800 early console use fix
This change removes printk's that occur before
console init is called.  In the best case, these
would cause an extremely slow boot, and in the
worst case would cause a complete post failure.

Change-Id: I50388e71225e95db602aa45835c39126c1c920a3
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/216
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-09-15 00:44:09 +02:00
efdesign98 0bcfff7908 AMD Agesa changes to fix F14 boot issues
This collection of changes fixes a buffer addressing
issue by removing one level of indirection, fixes an
Agesa HT mailbox retrieval bug, and fixes a buffer
location-by-signature issue.

Change-Id: Ic8a8cb3f9abddd9ad59343a85dbbee5aa7633be3
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/215
Reviewed-by: Marc Jones <marcj303@gmail.com>
Tested-by: build bot (Jenkins)
2011-09-15 00:24:00 +02:00
efdesign98 3f5ebd6533 AMD F14 Northbridge updates
This change is warning and whitespace fixes in the
northbridge code for AMD Family 14 rev C0 cpu update.
This does not address warnings in the mainboard,
Agesa, Cimx, or southbridge code.

Change-Id: I7ee7018a292ebb2343c9b7986dd21227185879dc
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/134
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-09-14 23:45:40 +02:00
efdesign98 99b6674bd2 Update to Asrock E350m1 for AMD F14 C0
This updates the E350m1 Agesa wrapper code to fix an
issue with AmdLateRunApTask.  It now passes the function
parameter through to the Agesa routine.  There is also
a change to the platform_cfg.h file that makes the
definition of BIOS_SIZE dependent on whether or not
it was defined earlier.

Change-Id: I19942c7d3ecd229a13ef0a69fa7e5b1ea0b909bf
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/139
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-09-14 22:59:14 +02:00
Kerry She 7b7b2c9ef9 mainboard: add avalue/eax-785 ITX mainboard
It's AM3 Socket, 880M + SB850 chipset, similar with advansus/a785e-i.
Onboard device UART, VGA, SATA, PCI Slot, 2 X16 PCIe slot, 4 X1 Pcie
slot, Lan, audio, PS2 keyboard/mouse and USB are verified.

Change-Id: I483363f5ff9fbfc5cda2f0521660751212f3e326
Signed-off-by: Kerry She <kerry.she@amd.com>
Signed-off-by: Kerry She <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/208
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-09-14 19:49:48 +02:00
Kerry Sheh 8c69b1d13b rs780: hide unused gfx ports and gpp ports
Hide the unused gfx ports and gpp ports if they are not configured as hotplug.
lspci -vvv will get more accurate information under Linux,
tested on avalue/eax-785e.

Change-Id: Iaabfd362a0a01f21d0f49aa2bd2d26f9259013fb
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/206
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-09-14 07:47:30 +02:00
Patrick Georgi a25828dd0e Provide mechanism to local additions to the build
site-local/ is an optional directory for local additions to the build.
If site-local/Makefile.inc exists it will be parsed and used.

Use it to define VGA option roms, splash screens, extra rules to the
tree...

Change-Id: I0c6ee43ffa40e6c3f193db081ab551ab75bc7478
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/212
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-09-14 07:44:25 +02:00
Mathias Krause 14b67f716d superiotool: Don't compile with -Werror
Older libpci version have headers using 'long long' which isn't allowed
in ANSI C. Since we cannot control the libpci version installed in the
system nor in generall have complete control over system headers, simply
skip using -Werror in our makefile.

Change-Id: Ibc1e57bef033bf4971f4108d078222dcf168d5e3
Signed-off-by: Mathias Krause <mathias.krause@secunet.com>
Reviewed-on: http://review.coreboot.org/210
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-09-14 07:43:33 +02:00
Mathias Krause 9beb5df3c4 inteltool: fixed 64 bit build
The inline assembly for cpuid() was 32 bit specific. Additionally a
format string referencing a size_t argument wasn't using the %z length
modifier.

Change-Id: Iac4a4d5ca81f9bf67bb7b8772013bf6c289e4301
Signed-off-by: Mathias Krause <mathias.krause@secunet.com>
Reviewed-on: http://review.coreboot.org/211
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-09-14 07:43:19 +02:00
Mathias Krause 5782fee0e1 inteltool: Fixed building of position independent executables
When building a position independent executable (PIE) EBX is used
internally by the compiler to generate position independent address
references so it cannot be used in the clobber list. Use the already
existing code for the Darwin plattform for that case, too -- it'll
preserve the EBX value.

Change-Id: Ief6d4872b8cd990856a0e8227a88bb228782aced
Signed-off-by: Mathias Krause <mathias.krause@secunet.com>
Reviewed-on: http://review.coreboot.org/209
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-09-14 07:43:04 +02:00
Patrick Georgi c230058199 libpayload: Add get_option_from()
This function allows reading the nvram configuration table from
locations other than the cbtable.

Change-Id: I56c9973a9ea45ad7bf0185b70d11c9ce5d0e0e1b
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/213
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-09-14 07:42:20 +02:00
QingPei Wang e169f82edf Add IT8721F support
only the serial port is tested, keyboard/mouse are gonna
to be tested later, it may also need some more patches
to make it work completely.

Change-Id: Ie9464d01c5d5760ebc800b3cd15a4ab2bad2e09f
Signed-off-by: QingPei Wang <wangqingpei@gmail.com>
Reviewed-on: http://review.coreboot.org/204
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-09-14 04:47:26 +02:00
Peter Stuge 864839a3e8 util/crossgcc: Update gdb to 7.3.1
The previous version is no longer available.

Change-Id: I8126617cfe9addeb4778f002398abbcb4c73d2c7
Signed-off-by: Peter Stuge <peter@stuge.se>
Reviewed-on: http://review.coreboot.org/214
Reviewed-by: Marc Jones <marcj303@gmail.com>
Tested-by: build bot (Jenkins)
2011-09-14 01:23:04 +02:00
Ruud Schramp bb41f50244 inteltool: added more device IDs
Change-Id: I6f2272ae4071025e671638e83bade6a96aac658b
Signed-off-by: Ruud Schramp <schramp@holmes.nl>
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/185
Tested-by: build bot (Jenkins)
2011-09-12 16:41:20 +02:00
Tobias Diedrich 4e22a3bc58 Add acpi_get_sleep_type() to i82371eb and P2B _PTS/_WAK methods
Build fix for src/arch/i386/boot/acpi.c if !CONFIG_SMP
Also check for acpi_slp_type 2 in acpi_is_wakeup, since S2
uses the same acpi wakeup vector as S3.
Add _PTS/_WAK methods to turn off/on the CPU/case fans and blink
the power LED while sleeping.
acpi_get_sleep_type() is in a seperate file i82371eb_wakeup.c because
it is used in both romstage and ramstage after patch 3/3, whereas
i82371eb_early_pm.c is used only in romstage.
I used the name acpi_get_sleep_type instead of  acpi_is_wakeup_early
because I think acpi_is_wakeup_early is a bit misleading as a name since it
doesn't return a boolean value.

Other chipsets so far only ever set acpi_slp_type to 0 and 3, so the
added check for acpi_slp_type == 2 (resume from S2) should not
change behaviour of other boards:
northbridge/intel/i945/northbridge.c:256:extern u8 acpi_slp_type;
northbridge/intel/i945/northbridge.c:263: acpi_slp_type=0;
northbridge/intel/i945/northbridge.c:267: acpi_slp_type=3;
northbridge/intel/i945/northbridge.c:271: acpi_slp_type=0;
southbridge/intel/i82801gx/i82801gx_lpc.c:171:extern u8 acpi_slp_type;
southbridge/via/vt8237r/vt8237r_lpc.c:149:extern u8 acpi_slp_type;
southbridge/via/vt8237r/vt8237r_lpc.c:238:  acpi_slp_type = ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0 ;
southbridge/via/vt8237r/vt8237r_lpc.c:239:  printk(BIOS_DEBUG, "SLP_TYP type was %x %x\n", tmp, acpi_slp_type);

Change-Id: I13feff0b8f49aa988e5467cdbef02981f0a6be8a
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/188
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-09-12 15:56:12 +02:00
efdesign98 78834b794d Miscellaneous AMD F14 warning fixes
This commit adds in some more fixes to AMD F14 compile
warnings.  The change in the mtrr.c file is in prep-
aration for changes yet to com, but it is currently
innocuous.

Change-Id: I6b204fe0af16a97d982f46f0dfeaccc4b8eb883e
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/133
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-09-12 14:55:24 +02:00
Noe Rubinstein 03169d3e1c Replace while with do; while to avoid repetition
Cosmetic only; replaces some 'while' loops with 'do; while' loops to
avoid repetition.

Replacement performed by the Ruby expression:
t.gsub!(/^(\s*)([^\n\{]+)\n\1(while[^\n\{;]+)\n\s*\2/,
	"\\1do \\2\n\\1\\3;")

Change-Id: Ie0a4fa622df881edeaab08f59bb888a903b864fd
Signed-off-by: Noe Rubinstein <nrubinstein@proformatique.com>
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/183
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-09-09 11:40:48 +02:00
Patrick Georgi ac624a638d Crank up CPU speed on Intel Core and Core2 CPUs
The CPUs start on their slowest speed, and were left that way by
coreboot. This change will speed up coreboot a bit, as well as
systems that don't change the clock for whatever reason.

Change-Id: Ia6225eea97299a473cf50eccc6c5e7de830b1ddc
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/176
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-09-09 11:40:30 +02:00
Stefan Reinauer 7981b940a6 Report GSE chipset and warn if the code has been compiled for the wrong chipset.
It would be nicer to unify the code so that it does all detection at runtime
instead of compile time (but that would also significantly increase code size)
so if someone else wants to give it a shot...

Change-Id: Idc67bdf7a6ff2b78dc8fc67a0da5ae7a4c0a3bf0
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/184
Tested-by: build bot (Jenkins)
2011-09-09 11:40:04 +02:00
Rudolf Marek 8679e52b96 Add support utils for tracing
Following patch adds a userspace util genprof
which is able to convert the console printed
traces to gmon.out file used by gprof & friends.
The log2dress will replace the adresses in logfile
with a line numbers.

Change-Id: I9f716f3ff2522a24fbc844a1dd5e32ef49b540c5
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/179
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-09-07 01:27:57 +02:00
Rudolf Marek 7f0e93060e Add support for the tracing infastructure in coreboot.
The compiler is forced to emmit special functions on every
entry/exit of the function. Add a compile time option
to support it. Function entries will be printed in
the console. The CONFIG_TRACE has more documentation.

Patch for userspace tools will follow.

Change-Id: I2cbeb3f104892b034c8756f86ed05bf71187c3f3
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/178
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-09-07 01:26:47 +02:00
Kerry She f73535c089 AMD F14 Rev C0 update
Add AMD Family14 Rev C0 cpu id

Change-Id: Iacd1c7b20e889da61a2085188766285f27e5c018
Signed-off-by: Kerry She <kerry.she@amd.com>
Signed-off-by: Kerry She <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/160
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-09-07 01:10:29 +02:00