If the AP actually needs to write to the TPM, then it is important and
the TPM should commit those changes to NVMEM immediately in case there
is an unexpected power loss (e.g. from a USB-C port partner reset upon
cold reboot request).
BRANCH=none
BUG=b:160913048
TEST=Verify that puff will no longer reboot loop when coreboot writes a
new Hmir (Hash mirror) in the TPM
Change-Id: I9597a55891d11bdf040d70f38b4c5a59c7888b8a
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43414
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
SataPortsEnableDitoConfig Enable DEVSLP Idle Timeout settings DmVal and
DitoVal. SataPortsDmVal and SataPortsDitoVal helps to determine when to
enter Device Sleep. Device Sleep enables the host bus adapter (HBA) to
assert the DEVSLP signal as soon as there are no commands outstanding
to the device and the port specific Device Sleep idle timer has expired.
Device Sleep Idle Timeout values (PxDEVSLP.DITO and PxDEVSLP.DM) are
port specific timeout values used by the HBA for determining when to
assert the DEVSLP signal. They provides a mechanism for the HBA to apply
a programmable amount of hysteresis so as to prevent the HBA from
asserting the DEVSLP signal too quickly which may result in undesirable
latencies. This patch is created based on Intel Tiger Lake Processor
PCH Datasheet with Document number:575857 and Chapter number:12.
* PxDEVSLP.DM -> SataPortsDmVal: Enable SATA Port DmVal DITO multiplier.
Default is 15.
* PxDEVSLP.DITO -> SataPortsDitoVal: Enable SATA Port DmVal DEVSLP Idle Timeout
(DITO), Default is 625ms.
BUG=b:151163106
BRANCH=None
TEST=Build and boot volteer and TGL RVP.
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Change-Id: I6a824524738a9e0609f54bea9d892b4a42a1d3db
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42214
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
0xc50, 0xc52, 0xc6f don't exist on Picasso. The PCI config space
registers define SATA and OHCI which are at the wrong bus locations.
I just remove the whole section since it's not used. We never access the
PCIe Error region, or the PM2 region either.
BUG=b:153001807, b:154756391
TEST=Build Trembyle
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I98aee09770f1df9f553c94580c1ee00c06a9cec1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
There is no reason to create a named variable. We can just return the
package.
BUG=b:153001807, b:154756391
TEST=None
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I4f8f0362adf5ea5f026d0ba5ac6ac917fa160142
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43423
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This PCI ID is required in order for JSL devices to perform SSDT
generation for DPTF.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I42209d15bc4f1654814465ce1412576f7349dddc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43421
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The ACPI specification, version 2.0 says:
_BFS is an optional control method.
So, remove them. They have been copy-pasted around quite a bit, and do
not do anything useful. Plus, it's deprecated in later ACPI versions.
Change-Id: I9ef21f231dd6051d410ac3a0fe554908409c2fa7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43443
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Turning the DXIO and DDI descriptor fields in the FSP_S_CONFIG struct
into arrays allows to properly iterate over the fields.
BUG=b:158695393
TEST=Mandolin still boots.
Change-Id: I85debe4d52399e933768b89b665ff10c9f7779f8
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43434
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Forgetting to add the #pragma pack() at the end of the header file can
lead to hard to debug breakage, so get rid of the #pragma pack usage and
add a __packed to the structs that need to be packed which has less
possibly unwanted side effects.
Since commit d44221f9c8 coreboot always
includes commonlib/compiler.h which provides __packed.
TEST=Timeless build results in identical binary.
Change-Id: Icc53168f4fbc3a63a859f686b18e7023d225f8d2
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Drop it before it grows moss.
Change-Id: I0b4f5487cca3c864ba531cc6c78a20c2682fc43d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43287
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Morphius cannot support 100Mhz fast SPI causing it to not boot.
Downgrade all zork boards to fast=66mhz and normal=33mhz to be safe.
BUG=b:161233767
TEST=Boot morphius
Change-Id: I7744dd0cb8dede985fbdc28a64385e0bc4048402
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43459
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Eric Peers <epeers@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Intel southbridges do this. Also make `acpi_sci_irq` non-static as it is
needed outside acpi.c with this change.
Change-Id: I2fd2ec5a3029dc1bd1fa65dc3d1af5505f1f1dad
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43377
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Intel southbridges do this. Also make `acpi_sci_irq` non-static as it is
needed outside acpi.c with this change.
Change-Id: I702988493e3b29d807a75c70485baaa2ff6d1aa2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43376
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Add USB ports, USB user-facing camera and USB bluetooth to devicetree.
USB ports 4 and 5 are duplicated for picasso and dali.
BUG=b:158096224
TEST=Boot Trembyle and Dalboz, Dump acpi tables
Change-Id: Icf8628d91e27a3afdc5fd67a53b44089c809da87
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Split zork baseboard devicetree between dalboz and trembyle.
The devicetree is simply duplicated, no other changes in this commit.
BUG=b:158096224
TEST=Build coreboot for zork
Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I5b26770790092c69db9567fa4337edd21a6ed809
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Screen flickered on VT2 on some devices after idle a period of time.
Remove SSR (1/8) setting for SA to default SSR (1/2), screen flicking
issue disappeared, and didn't affect acoustic noise much.
Because CB:38212 (commit eae254e) caused this issue.
BUG=b:160754994
TEST=build dratini, observe that screen flick issue disapppered
Change-Id: I9e81c2f15dd6babfa360eee213fc4ab6310c7455
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43284
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
SaGv needs to be enabled for only QS. On ES2, we are seeing system
instability.
BUG=b:159198381
TEST=Tested for boot. Power and performance tests were run with
volteer2 with qs setup. System showed stability.
Tested for boot stability on on delbin.
Change-Id: I1bce3b9f837fb19ba5a20ae31750a73474a86788
Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42483
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Configure volteer2 and delbin, the two variants currently using
preQS or QS silicon, to use CSE Lite.
BUG=b:158140797
TEST=cd to volteer's asset_generation folder, execute
"./gen_all_variant_images.sh" and verify that all variant
images are produced.
Change-Id: I5e444529b090d82094b9da0df2648ea4cdb2888e
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43413
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Extract DRAM info from AMD_FSP_DMI_HOB and store it as mem_info in
cbmem with id CBMEM_ID_MEMINFO. Subsquently extract mem_info objects
from cbmem to build SMBIOS type 17 tables.
BUG=b:148277751,b:160947978
TEST=dmidecode -t 17
BRANCH=none
Change-Id: Iacedbb017d19516674070f89ba0aa217f55383e3
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
CB:43224 ("mb/google/zork: Add helpers for v3 schematics and wifi
power enable") added helper functions for determining if a board uses
v3 schematics. However, it introduced a regression by adding a wrong
check for variant_uses_v3_schematics() in variant_audio_update(). This
change fixes the check to ensure that dmic_gpio is updated when
variant is not using v3 schematics.
BUG=b:161141258,b:161128964
TEST=Verified on trembyle that trackpad works again (it was broken
because of the regression).
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I0e6ad844f68cface7b545f1547bd94470c30dde4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43415
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Create the woomax variant of the zork reference board by copying
the template(coreboot-zork/util/mainboard/google/trembyle)
files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.1.1).
BUG=b:158343602
BRANCH=None
TEST=emerge-zork coreboot
Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: I0bb8ce1851f4064d24e48fd8957e2f9fe1e80b53
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Karthikeyan Ramasubramanian