Commit graph

967 commits

Author SHA1 Message Date
Vladimir Serbinenko
113a366848 Add GRUB2 payload to build system
Since a long time GRUB 2 is a viable payload alternative to SeaBIOS and
FILO. So make it easy for coreboot users to use GRUB 2 as a payload by
integrating it into coreboot’s build system, so it can be selected in
Kconfig.

As the last GRUB 2 release 2.00 is too old and has several bugs when
used as a coreboot payload only allow to build GRUB 2 master until a new
GRUB release is done. The downside is, that accidental breakage in
GRUB’s upstream does not affect coreboot users.

Currently the GRUB 2 payload is built with the default modules which
results in an uncompressed size of around 730 kB. Compressed it has a
size of 340 kB, so it should be useable with 512 kB flash ROMs.

Tested with QEMU.

Change-Id: Ie75d5a2cb230390cd5a063d5f6a5d5e3fab6b354
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4058
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-11-19 01:07:25 +01:00
Gerd Hoffmann
06262743c7 smbios: make manufacturer, product_name and uuid runtime settable
Make manufacturer, product_name and uuid smbios fields (type 1)
configurable at runtime, simliar to version and serial number.

Change-Id: Ibc826225e31fa42aa944fa43632dd6a406d5c85d
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/4085
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-11-18 12:49:29 +01:00
Gerd Hoffmann
a91daa5ba1 add memory clobber to ins{b,w,l}
Change-Id: Ia710eb59f23a52afba2a8ef6e0ff2b2306107245
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/4033
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-11-10 20:41:52 +01:00
Andrew Wu
cd9abf95e7 arch/x86/Makefile.inc: Pass $(AS) and $(CPP) to SeaBIOS
SeaBIOS’ Makefile requires cpp (C Preprocessor) to build. Modify
the xcompile script to search for cpp program path, and pass it to
SeaBIOS’ `Makefile.inc`. Also pass the program path for as (GNU assembler).

This is needed, so the crossgcc toolchain to build the SeaBIOS payload
under Mac OSX. OSX ships a cpp program, but it works differently
from GNU CPP, so we need to override it.

Change-Id: If996ffbb76ec4bd16079b54b41f3fac07bfe25be
Signed-off-by: Andrew Wu <arw@dmp.com.tw>
Reviewed-on: http://review.coreboot.org/3896
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
2013-10-17 01:59:50 +02:00
Kyösti Mälkki
697927cc35 CBMEM: Define cbmem_top() just once for x86
It is expected this will always be a casted get_top_of_ram() call
on x86, no reason to do that under chipset.

Change-Id: I3a49abe13ca44bf4ca1e26d1b3baf954bc5a29b7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3972
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-10-15 13:18:22 +02:00
Kyösti Mälkki
2644793ef4 Have option of timestamps, CBMEM console and usbdebug for most boards
As boards without EARLY_CBMEM_INIT do not initialize CBMEM in romstage,
and have no CAR migration, these features are available for ramstage only.

Change-Id: Ic3f77ccdedd4e71ba693619c02c9b98b328a0882
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3970
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-10-15 13:15:18 +02:00
Kyösti Mälkki
082c19ea89 CBMEM: Fail builds on missing get_top_of_ram()
Dummy get_top_of_ram() is removed from romstage to fail already at
build-time for cases where cbmem_initialize() would not complete.

The mechanisms behind CAR_GLOBAL migration only work correctly when
romstage can succesfully make the cbmem_initialize() call.

Change-Id: I359820fb196ef187b9aa2e8a3e8f658a0550f237
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3969
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-10-15 13:14:57 +02:00
Kyösti Mälkki
f8bf5a10c5 Revert "CBMEM: Always have early initialisation"
This reverts commit de1fe7f655.

While things appeared to work, there were actually invalid references
to CAR storage after CAR was torn down on boards without
EARLY_CBMEM_INIT. It was discussed use of CAR_GLOBAL should be
restricted to boards that handle CAR migration properly.

Change-Id: I9969d2ea79c334a7f95a0dbb7c78065720e6ccae
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3968
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-10-14 17:16:22 +02:00
Stefan Reinauer
fd4f4136e8 Rename cpu/x86/car.h to arch/early_variables.h
and add an ARMv7 version.

Change-Id: I14fbff88d7c2b003dde57a19bf0ba9640d322156
Signed-off-by: Stefan Reinauer <reinauer@google.com>
[km: rebased fa004acf8 from chromium git]
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3939
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2013-10-13 12:47:05 +02:00
Kyösti Mälkki
cbf5bdfe67 CBMEM: Always select CAR_MIGRATION
If romstage does not make cbmem_initialize() call, linker should
optimize the code for CAR migration away.

This simplifies design of CBMEM console by a considerable amount.
As console buffer is now migrated within cbmem_initialize() call there
is no longer need for cbmemc_reinit() call made at end of romstage.

Change-Id: I8675ecaafb641fa02675e9ba3f374caa8e240f1d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3916
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-21 06:34:55 +02:00
Kyösti Mälkki
a2f6af3330 ROMCC boards: Fix builds with CBMEM console, timestamps or usbdebug
These features depend on CAR_GLOBAL region, which is not available
when romstage is built with ROMCC. Exclude these from romstage, keep
them available for ramstage.

A follow-up patch will fix the dependencies and allows enabling these
features in menuconfig.

Change-Id: I9de5ad41ea733655a3fbdc734646f818e39cc471
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3919
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-21 06:22:33 +02:00
Gabe Black
4938a329ee ARM: Add some missing dependencies on config.h to ARM's Makefile.inc.
These dependencies came indirectly through kconfig.h which was included
automatically with a -include option which was either part of INCLUDES or
specified directly. With this change, I'm able to build for beaglebone with
make -j 48.

Change-Id: Ib57d0c6a755b747165b235c2328c3c30bd6dd67d
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3922
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-09-17 01:00:12 +02:00
Kyösti Mälkki
bc90e15d3f CBMEM: Backup top_of_ram instead of cbmem_toc
AMD northbridges have a complex way to resolve top_of_ram.
Once it is resolved, it is stored in NVRAM to be used on resume.

TODO: Redesign these get_top_of_ram() functions from scratch.

Change-Id: I3cceb7e9b8b07620dacf138e99f98dc818c65341
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3557
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-11 07:18:02 +02:00
Kyösti Mälkki
c04afd6433 CBMEM: Add cbmem_locate_table()
For both romstage and ramstage, this calls an arch-specific function
get_cbmem_table() to resolve the base and size of CBMEM region. In ramstage,
the result is cached as the query may be relatively slow involving multiple PCI
configuration reads.

For x86 CBMEM tables are located right below top of low ram and
have fixed size of HIGH_MEMORY_SIZE in EARLY_CBMEM_INIT implementation.

Change-Id: Ie8d16eb30cd5c3860fff243f36bd4e7d8827a782
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3558
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-11 07:17:14 +02:00
Kyösti Mälkki
e1ea802ea6 CBMEM tables: Remove references to global high_tables_base
Unify checks and writing of CBMEM tables for x86 and ARMv7.

Change-Id: I89c012bce1b86d0710748719a8840ec532ce6939
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3559
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-11 07:15:10 +02:00
Kyösti Mälkki
1ae305efe1 CBMEM: Add cbmem_late_set_table() and drop references to high_tables_base
This helper function is for compatibility only for chipsets that do
not implement get_top_of_ram() to support early CBMEM.

Also remove references to globals high_tables_base and _size under
arch/ and from two ARMv7 boards.

Change-Id: I17eee30635a0368b2ada06e0698425c5ef0ecc53
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3902
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-11 07:12:15 +02:00
Kyösti Mälkki
2b790f6512 CBMEM AMD: Fix calls to set_top_of_ram_once()
We can postpone the call to set_top_of_ram_once() outside the
loops and make just one call instead.

As set_top_of_ram() is now only called once, it is no longer
necessary to check if high_tables_base was already set.

Change-Id: I302d9af52ac40c7fa8c7c7e65f82e00b031cd397
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3895
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-09-11 07:09:21 +02:00
Kyösti Mälkki
e7e847cd5c CBMEM AMD: Remove references to global high_tables_base
Prepare for removal of globals high_tables_base and _size
by replacing the references with a helper function.

Added set_top_of_ram_once() may be called several times,
but only the first call (with non-zero argument) takes effect.

Change-Id: I5b5f71630f03b6a01e9c8ff96cb78e9da03e5cc3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3894
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-11 07:06:15 +02:00
Patrick Georgi
16ae95c4bc Add Kconfig options for Linux as payload
These allow to define a kernel image, initrd and command line.

Change-Id: I40155b812728a176b6d15871e1e6c96e4ad693c8
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/3893
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2013-08-31 08:58:39 +02:00
Kyösti Mälkki
842f0bab04 Add pnp_devfn_t and use with __SIMPLE_DEVICE__
Declare the functions that may be used in both romstage and ramstage
with simple device model. This will later allow to define PNP access
functions for ramstage using the inlined functions from romstage.

Change-Id: I2a0bd8194acaf9c4c7252a29376eec363397e3a6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3871
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-08-24 07:38:03 +02:00
Kyösti Mälkki
3f9a62e5ad Add pci_devfn_t and use with __SIMPLE_DEVICE__
Declare the functions that may be used in both romstage and ramstage
with simple device model. This will later allow to define PCI access
functions for ramstage using the inlined functions from romstage.

Change-Id: I32ff622883ceee4628e6b1b01023b970e379113f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3508
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-08-24 07:37:12 +02:00
Kyösti Mälkki
361cd8153d console: Squelch console output from AP CPUs in romstage
Add Kconfig option SQUELCH_EARLY_SMP and have it enabled by
default.

Console drivers have unpredictable results if multiple threads
attempt to share same resources without spinlock. Serial UARTs
have not had huge problems, only distorted output, but those
relying on cache-as-ram (CBMEM and usbdebug) may require this.

Change-Id: I7f406fdea7b6dc6a341c4da2fab56f7b7ff568b4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3854
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-08-16 05:39:47 +02:00
Peter Stuge
f040858ec3 payload/SeaBIOS: Add SEABIOS_PS2_TIMEOUT Kconfig variable
This allows mainboards to preconfigure a ps2-keyboard-spinup
timeout when SeaBIOS is chosen as the payload.

The Kconfig option can be changed manually if CONFIG_EXPERT is set.

Change-Id: I5732b18ef04f4bdef6236f35039656ad02011aec
Signed-off-by: Peter Stuge <peter@stuge.se>
Reviewed-on: http://review.coreboot.org/3734
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-08-15 20:46:21 +02:00
Siyuan Wang
3e32cc00d1 AMD Kabini: Add northbridge AGESA wrapper (new AMD processor)
src/arch/x86/boot/tables.c and src/include/device/pci_ids.h are also
changed because these two files depend on F16kb northbridge macros

Change-Id: Iedc842f0b230826675703fc78ed8001a978319c5
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-by: Bruce Griffith <bruce.griffith@se-eng.com>
Tested-by: Bruce Griffith <bruce.griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/3782
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-08-05 18:23:34 +02:00
Kyösti Mälkki
ef84401149 Add directive __SIMPLE_DEVICE__
The tests for __PRE_RAM__ or __SMM__ were repeatedly used
for detection if dev->ops in the devicetree are not available
and simple device model functions need be used.

If a source file build for ramstage had __PRE_RAM__ inserted
at the beginning, the struct device would no longer match the
allocation the object had taken. This problem is fixed by
replacing such cases with explicit __SIMPLE_DEVICE__.

Change-Id: Ib74c9b2d8753e6e37e1a23fcfaa2f3657790d4c0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3555
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-08-01 15:57:11 +02:00
Kyösti Mälkki
aad0747216 Redefine pci_bus_default_ops as function
Taking device_t as a parameter, this allows to alter the PCI config
access handlers. This is useful to add tracing of PCI config writes
for devices having problems to initialise correctly.

On older AMD platform PCI MMIO may not be able to fully configure all
PCI devices/nodes, while MMIO_SUPPORT_DEFAULT would be preferred due
to its atomic nature. So those can be forced to IO config instead.

Change-Id: I2162884185bbfe461b036caf737980b45a51e522
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3608
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-07-25 11:35:58 +02:00
Ronald G. Minnich
b5e777c433 X86: make the SIPI num_starts a config variable
The code to figure out how to set num_starts was
starting to get kludgy. It's a constant for a given
CPU; constants should be constant; make it a config variable.

This change includes an example of how to override it.
Build but not boot tested; drivers welcome.

Change-Id: Iddd906a707bb16251615c7b42f2bfb5a044379b4
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/3796
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2013-07-22 20:46:51 +02:00
Gabe Black
978c215127 ARM: Define custom ELF headers for ARM.
At least when building with the gnu toolchain, the headers the linker
automatically generate save space for the actual ELF headers in one of the
loadable segments. This creates two problems. First, the data you intended to
be at the start of the image doesn't actually show up there, it's actually the
ELF headers. Second, the ELF headers are essentially useless for firmware
since there's currently nothing to tell you where they are, and even if there
was, there isn't much of a reason to look at them. They're useful in userspace
for, for instance, the dynamic linker, but not really in firmware.

This change adds a PHDRS construct to each of the linker scripts used on ARM
which define a single segment called to_load which does not have the flag set
which would tell the linker to put headers in it. The first section defined in
the script has ": to_load" to tell the linker which segment to put it in, and
from that point on the other sections go in there by default.

Change-Id: I24b721eb436d17afd234002ae82f9166d2fcf65d
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3580
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-15 18:33:41 +02:00
Peter Stuge
c392b6477f SMBIOS: Add smbios_write_type11() for creating an OEM Strings structure
Change-Id: Id338968429435bac26595c4843b07cdbb91dd64d
Signed-off-by: Peter Stuge <peter@stuge.se>
Reviewed-on: http://review.coreboot.org/3618
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-15 17:06:23 +02:00
Peter Stuge
4e7385b58f SMBIOS: Allow overriding default Manufacturer and Product names
The vendor and part name from coreboot is normally stored in these
SMBIOS structure fields, but it can be useful to override them.

On Lenovo ThinkPads an override is e.g. needed to convince the Linux
thinkpad_acpi.c driver that it is actually running on a ThinkPad.

Change-Id: I0dfe38b9f6f99b3376f1547412ecc97c2f7aff2b
Signed-off-by: Peter Stuge <peter@stuge.se>
Reviewed-on: http://review.coreboot.org/1556
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2013-07-14 23:44:10 +02:00
Gabe Black
7a6651ceb3 arm: Add and enable an arch specific version of memmove.
This version is taken from arch/arm/lib/memmove.S in the Linux kernel.

Change-Id: Ic875d0cf5b1cb407606530b7f465c406b134f0fa
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3763
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-14 20:36:00 +02:00
Gabe Black
ccdc005b01 x86: Add and enable an arch verson of memmove.
This is from memcpy_32.c in the Linux kernel. There was no copyright header
in the original file either.

Change-Id: Ifd259cb8a87615dce79ed1e551cc4bacb0414b4f
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3762
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-14 20:35:24 +02:00
Gabe Black
5fbfc911c1 Move the HAVE_ARCH_* config options from src/arch/x86 to src/.
The options that keep track of whether there are arch versions of the standard
string functions shouldn't be in the arch/x86 directory since they apply to
all architectures. Move them into the higher level, shared Kconfig defaulting
to off. Then, in each applicable arch (currently all of them) they can be
selected to on.

Change-Id: I7ea64a583230fdc28773f17fd7cc23e0f0a5f3d6
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3760
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-11 17:55:36 +02:00
Gabe Black
db02069d71 arm: Add a W() macro for use in kernel assembler.
Some kernel assembly code uses a W macro to optionally add a .w to
instructions that need to be 32 bit thumb. The gnu assembler doesn't seem to
need the .w and won't assemble if it's provided.

Change-Id: I0a288177788b5c61810ee7bd3d2debea66835de2
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3759
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-11 17:55:05 +02:00
Kyösti Mälkki
b25a9da6e7 Unify PCI configuration cycles
Split PCI IO configuration and MMIO configuration cycles to separate
files. Modern hardware does not use IO cycles for PCI configuration
after initial setup in bootblock.

Note that the pci_mmio_ and pcie_ functions were different in masking
the alignment for register address. PCI standard requires that 16-bit
and 32-bit configuration register writes do not cross boundaries.

Change-Id: Ie6441283e1a033b4b395e972c18c31277f973897
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3554
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-07-11 01:43:19 +02:00
Kyösti Mälkki
33e5df3f25 Set PCI bus operations at buildtime for ramstage
PCI bus operations are static through the ramstage, and should be
initialized from the very beginning. For all the replaced instances,
there is no MMCONF_SUPPORT nor MMCONF_SUPPORT_DEFAULT selected for
the northbridge, so these continue to use PCI IO config access.

Change-Id: I658abd4a02aa70ad4c9273568eb5560c6e572fb1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3607
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-11 01:29:35 +02:00
Kyösti Mälkki
9e7806a788 usbdebug: Move ehci_debug_info allocation
Move ehci_debug_info allocation from console to lib, as console code
was only built for ramstage.

Implement dbgp_ehci_info() to return the EHCI context. Alread alias this
as dbgp_console_input() and _output() to return the console stream context
later on.

Change-Id: Id6cc07d62953f0466df61eeb159e22b0e3287d4e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3625
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 23:23:55 +02:00
Stefan Reinauer
9d9b0dd209 Don't try to use CBMEM console in bootblock
Otherwise we have to worry about hand off between bootblock and
romstage. Too much complexity

Change-Id: I89bf8a229dba7e1330accadf9a732d831ebc4827
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3694
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 22:44:42 +02:00
Stefan Reinauer
6b0bab916a ARMv7: Drop duplicate call to bootblock_cpu_init()
This is already called in ARMv7 bootblock_simple.c so we don't
want to do it twice

Change-Id: I80cb41035b8a77787e04f2ea58a1cd372cea97d8
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3692
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 22:44:06 +02:00
Gabe Black
b919809afe ARM: Don't leave alignment checking on after the exception test.
Currently, the exception handling code on ARM turns on alignment checks as an
easy way to generate an exception for testing purposes. It was leaving it on
which disabled unaligned accesses for other, unlreated code running later.
This change adjusts the code so the original value of the alignment bit is
restored after the test exception.

Change-Id: Id8d035a05175f9fb13de547ab4aa5496d681d30c
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3690
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 22:43:16 +02:00
Hung-Te Lin
2867060098 arm: Fix memory barrier usage in IO operation
The dmb should be executed before reading operations, and before/after writing
operations.

Change-Id: I572136a2f9a07eb2c38a112f5deeb2de0c0fd46c
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3682
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 22:36:33 +02:00
Stefan Reinauer
ff7c8e82d1 armv7a: Enable native memcpy / memset
The code has been there for quite a while but was never enabled.

Change-Id: I4ec3dcbb3c03805ac5c75872614e5d394df667cf
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3675
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 21:50:14 +02:00
Gabe Black
001056f560 ARM: Tell the linker memset and memcpy are functions.
The memset and memcpy functions are assembled as ARM code, likely because
that's the default of the assembler. Without special annotation, the assembler
and linker don't know that those symbols are functions which need special
handling so that ARM/thumb issues are handled properly. This change adds that
annotation which gets those functions working in Coreboot which is compiled as
thumb. Libpayload and depthcharge are compiled as ARM so they don't *need* the
annotation since it just works out in ARM mode, but it's the safe thing to do
in case we change that in the future.

We should explicitly select ARM vs. thumb when assembling assembly files to be
consistent across builds and toolchains.

Change-Id: I814b137064cf46ae9e2744ff6c223b695dc1ef01
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3672
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 21:49:45 +02:00
Gabe Black
fbb11cf979 ARM: Separate the early console (romstage) from the bootblock console.
It might be that you want an early console in romstage before RAM is up, but
you can't or don't want to support the console all the way back in the
bootblock. By making the console in those two different environments
configurable seperately that becomes possible.

On the 5250 console output as early as the bootblock works, but on the 5420 it
only starts working in the ROM stage after clocks have been initialized.

Change-Id: I68ae3fcb4d828fa8a328a30001c23c81a4423bb8
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3671
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 21:47:52 +02:00
Stefan Reinauer
37332b66fa arch: clean up Kconfig and Makefile
remove some unused code

Change-Id: I41602fb391c1910c588a4f9dcc7c2edefe8ab5bc
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3669
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 21:47:27 +02:00
Hung-Te Lin
d63bddc499 armv7: Reserve space BL1 and checksum header by specifying bootblock offset.
Not all ARM systems need "BL1", and the layout of BL* and bootblock may be
different (ex, Exynos 5250 may use a new BL1 with variable length checksum
header).

To support that better, define the real base address (and ROM offset) of boot
block, and then we can post-processing ROM image file by filling data / checksum
and any other information.

Change-Id: I0e3105e52500b6b457371ad33a9aa546acf28928
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3664
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 21:46:01 +02:00
Aaron Durbin
32ab283b10 cpu: Add CPU microcode file to cbfs with 16-byte alignment
On x86 there is a 16-byte alignment requirement for the
addresses containing the CPU microcode. The cbfs files
containing the microcode are used in memory-mapped fashion
when loading new mircocode. Therefore, the data payload's
address/offset of a cbfs file in flash dictates the resulting
alignment. Fix this by processing the CPU microcode cbfs
file separately as it uses $(CBFSTOOL) to find the proper
location within the provided rom image.

Change-Id: Ia200d62dbcf7ff1fa59598654718a0b7e178ca4c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3663
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 21:45:28 +02:00
Stefan Reinauer
e8b08ba47c Drop ELF remains from boot code
This stuff is not used, so let's drop it.

Change-Id: I671a5e87855b4c59622cafacdefe466ab3d70143
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3660
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 21:43:55 +02:00
Stefan Reinauer
93ce3b3a28 ARMv7: flatten arch/armv7 source tree
With only 19 source files it doesn't make a whole lot of sense to
create sub directories in arch/armv7, especially since the files
were distributed somewhat randomly.

Change-Id: I029c7848e915edf1737e1c401c034837c95d179d
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3659
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 21:43:38 +02:00
Gabe Black
800790d4e1 ARM: Fix up page table/cachability management.
When modifying the page tables, use writel to ensure the writes happen, flush
the page tables themselves to ensure they're visible to the MMU if it doesn't
look at the caches, and invalidate the right TLB entries.

The first two changes are probably safer but may not be strictly necessary.
The third change is necessary because we were invalidating the TLB using i
which was in megabytes but using an instruction that expects an address in
bytes.

One symptom of this problem was that the framebuffer, which was supposed to be
marked uncacheable, was only being partially updated since some of the updates
were still in the cache. With this change the graphics show up correctly.

Change-Id: I5475df29690371459b0d37a304eebc62f81dd76b
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3653
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 21:06:34 +02:00