Commit Graph

51879 Commits

Author SHA1 Message Date
Felix Held ff01442fc3 soc/amd/picasso/Kconfig: update VGA_BIOS_ID's help text
map_oprom_vendev_rev is implemented in graphics.c in the SoC directory.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0123cb8ff662445fd0a613711d9e1981272b1235
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73052
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-16 16:08:47 +00:00
Eric Lai d47a104a2d mb/google/brya: Add new baseboard hades with variants hades
Add a new baseboard for hades, an Intel RPL based reference design.
Also, add variants for the reference boards hades. This commit is
a stub which only adds the minimum code needed for a successful build.
Need update gpio and memory DQ pins after final shchematic comes out.

BUG=b:269371363
TEST=abuild -a -x -c max -p none -t google/brya -b hades

Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Ib7fbdf997df8225cc7814a34f8b4e4e04884dbf9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2023-02-16 15:22:21 +00:00
Fred Reitberger 1fcd7f066d soc/amd/mendocino: Remove non-functional APCB check
The way the PSP_APCB_FILES list is created will always insert at least a
space into it. When tested by the if, this space will prevent the else
clause from ever running and never generate a build error.

Remove the non-functional check. Instead, mainboards should select
warn_no_apcb or die_no_apcb to generate a warning message or build error
if the APCB is missing.

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Ic96846d74df2dc279e13b22f2a83b6f893954fe8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73009
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-16 15:21:56 +00:00
Fred Reitberger 0dab798786 soc/amd/glinda: Remove non-functional APCB check
The way the PSP_APCB_FILES list is created will always insert at least a
space into it. When tested by the if, this space will prevent the else
clause from ever running and never generate a build error.

Remove the non-functional check. Instead, mainboards should select
warn_no_apcb or die_no_apcb to generate a warning message or build error
if the APCB is missing.

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I26b96966495dc35a8b4a0cb7d5a841f3812f2a70
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73007
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-16 15:21:02 +00:00
Fred Reitberger 2cd8fa7a0f soc/amd/phoenix: Remove non-functional APCB check
The way the PSP_APCB_FILES list is created will always insert at least a
space into it. When tested by the if, this space will prevent the else
clause from ever running and never generate a build error.

Remove the non-functional check. Instead, mainboards should select
warn_no_apcb or die_no_apcb to generate a warning message or build error
if the APCB is missing.

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Ib9fe0f05739fb19da2494629dc1d5aaa0ca6431f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73006
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-16 15:19:05 +00:00
Fred Reitberger 38954e2461 soc/amd/common: Add die_no_apcb
Add target to die when no APCB is found. This is not always a fatal
case, so mainboards can select between this and warn_no_apcb.

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I5bbc8dd3200c4781677411e67a4b5f1fe8b20286
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73005
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-02-16 15:18:41 +00:00
Yidi Lin 23942e221d mb/google/geralt: Pass XHCI_INIT_DONE to the payload
BUG=b:269059211
BRANCH=none
TEST=emerge-gralt coreboot

Change-Id: Ia2ec6db332939f1ac629cda9a0784a12c92d91da
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73056
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
2023-02-16 15:06:27 +00:00
Yidi Lin bd6b81dcad vboot: Add VBOOT_ARMV8_CE_SHA256_ACCELERATION config
Add Kconfig option for VBOOT_ARMV8_CE_SHA256_ACCELERATION, which will
use ARMv8 Crypto Extension for SHA256[1] instead of software
implementation.

This will speed up firmware verification in verstage.

[1] https://crrev.com/c/4170144

BUG=b:263514393
BRANCH=corsola
TEST='calculating body hash (SHA2)' get 13 msecs improvement on
Tentacruel.
Before:
 509:finished calculating body hash (SHA2)             161,548 (14,490)

After:
 509:finished calculating body hash (SHA2)             155,101 (1,187)

Change-Id: I02671338fd9e0deb5294dbb7c03528061edc18c4
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72711
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-16 15:04:40 +00:00
Yidi Lin 70409217e7 libpayload: Add VBOOT_SHA_ARMV8_CE config
Add Kconfig option for VBOOT_SHA_ARMV8_CE, which will use ARMv8 Crypto
Extension for SHA256[1] instead of software implementation.

[1] https://crrev.com/c/4170144

BUG=b:263514393
BRANCH=corsola
TEST='vboot kernel verification' gets 111 msecs improvement on
Tentacruel.
Before:
1100:finished vboot kernel verification                905,150 (123,518)

After:
1100:finished vboot kernel verification                787,277 (12,254)

Cq-Depend: chromium:4170144, chromium:4242678
Change-Id: If92830830a0658dfad2a066e9efa624783865cf2
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72710
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-02-16 15:04:24 +00:00
Yidi Lin 458f1720f1 Update vboot submodule to upstream main
Updating from commit id ffb34f48:
    PRESUBMIT: disable automatic git cl presubmit

to commit id 5b8596ce:
    2sha256_arm: Fix data abort issue

This brings in 15 new commits.

Change-Id: I27a2dbd83114d7f5c075e0823f0c7948b82da694
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73058
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-02-16 15:03:13 +00:00
Cliff Huang aa5e362537 mb/intel/adlrvp: Fix RTD3 timing for PCIe slot1
Fix RTD3 timing for adlrvp_p_ext_ec and adlrvp_rpl_ext_ec.

BUG=none
BRANCH=firmware-brya-14505.B
TEST=Insert a SD card or NIC AIC on PCIe slot1 and run
'suspend_stress_test -c 1'. The RP8 should not cause suspend issue.

Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I792c55a6361d1eae55cc6f668a03dc2503120fe1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72422
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-16 14:13:09 +00:00
Cliff Huang 0539962835 soc/intel/common/block/pcie/rtd3: Fix root port _ON logic
_ON() calls _STA() at the beginning. If _STA() indicates the device is
ON, it exits immediately.  The solution is to move this _STA() check
into the ONSK logic. In general cases, ONSK remains '0'.

NOTE: RTD3 provides a way to skip _OFF() and _ON() methods following
by a device reset such as WWAN device. When such device calls its
_RST(), it increments OFSK. When the following _OFF() is called, it
was scheduled to skip, it will also increments ONSK. Similarly, when
the following _ON() is called, it checks if the previous _OFF was
skipped or not. If skipped, it needs to do the same. In normal
suspend/resume cases, these two variables remains '0'. No _OFF() and
 _ON() calls are skipped.

entire generated code:

Method (_ON, 0, Serialized)  // _ON_: Power On
{
    If ((ONSK == Zero))
    {
        Local0 = \_SB.PCI0.RP01.RTD3._STA ()
        If ((Local0 == One))
        {
            Return (One)
        }

        Acquire (\_SB.PCI0.R3MX, 0xFFFF)
        EMPG = Zero
        Local7 = 0x06
        While ((Local7 > Zero))
        {
            If ((AMPG == Zero))
            {
                Break
            }

            Sleep (0x10)
            Local7--
        }

        Release (\_SB.PCI0.R3MX)
        \_SB.PCI0.PMC.IPCS (0xAC, Zero, 0x10, 0x00000020, 0x00000020,
          0x00000020, 0x00000020)
        \_SB.PCI0.STXS (0x015E)
        If ((NCB7 == One))
        {
            L23R = One
            Local7 = 0x14
            While ((Local7 > Zero))
            {
                If ((L23R == Zero))
                {
                    Break
                }

                Sleep (0x10)
                Local7--
            }

            NCB7 = Zero
            Local7 = 0x08
            While ((Local7 > Zero))
            {
                If ((LASX == One))
                {
                    Break
                }

                Sleep (0x10)
                Local7--
            }
        }
    }
    Else
    {
        ONSK--
    }
}

BUG=b:249931687
BUG=b:241850118
TEST=Use above functions and check the generated SSDT table after OS
boot.

Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: Id1ea2e78e98d334a90294ee6cdd14ae2de9b9b62
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72826
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Kane Chen <kane.chen@intel.corp-partner.google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-16 14:12:07 +00:00
Tim Chu 3c31173c1c soc/intel/xeon_sp: add ebg (Emmitsburg PCH) directory
EBG (Emmitsburg) PCH is used in Intel SPR-SP chipset.

These changes are in accordance with the documentation:
* Intel(R) Emmitsburg Platform Controller Hub External Design
Specification. Document Number: 606161
* Emmitsburg PCH BIOS Specification. Document Number: 631063.

Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: I393c1df75a344519fca7d680116f41f5f8bd9e87
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71945
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2023-02-16 14:07:15 +00:00
Zheng Bao 5e9e7bff4b mb/amd/birman&mayan: Use relative address as EC FW location
When the flash size is over 16M, the absolute address could be lager
than 16M, which can not be taken by CBFS. For the relative address, it
is more flexible.

This is one of series of patches to support 32/64M flash.
BUG=b:255374782

TEST=binary identical test on birman and mayan when
CONFIG_BIRMAN_HAVE_MCHP_FW and CONFIG_MAYAN_HAVE_MCHP_FW are set as
y.

Change-Id: I65be3039cd3449bfb481ad87281b72e88a58bd45
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72960
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-16 14:02:42 +00:00
Johnny Lin db0946239f mb/ocp/deltalake: Set SMM console log level via VPD
Select DEBUG_SMI and RUNTIME_CONFIGURABLE_SMM_LOGLEVEL.

Tested=On OCP Delta Lake, SMM log level can be changed via VPD variable.

Change-Id: I73afc944fbd6c21e884397f3049bd363e2c1ce2c
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47006
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2023-02-16 00:48:04 +00:00
Johnny Lin 9fb89e33bc drivers/ocp/vpd: Override mainboard_set_smm_log_level
VPD variable 'smm_log_level' can be read and passed to SMM for
overriding SMM log level. By default it's zero therefore it disables
most of the SMM log. When we need to see SMM log we can set this VPD
to a larger value to enable it.

Implement mainboard_set_smm_log_level() that reads VPD variables for SMM
log level.

Change-Id: I90d471d1d070d9a0f1a82ca9da8a2c034c9fd574
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71992
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2023-02-16 00:47:11 +00:00
Subrata Banik be0590c3e1 soc/intel/cmn/gfx: Skip warning msg in ChromeOS normal mode
This patch ensures avoiding displaying wrong warning msg as
`Graphics hand-off block not found` during ChromeOS normal mode
booting as FSP is not executing GFX PEIM hence, GFX hand-off HOB
is expected to be missing. 

TEST=Able to build and boot google/rex in normal mode w/o having
warning msg. 

Change-Id: Ia9192129852195f6183c0c43369cd33b253f9140
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73028
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2023-02-16 00:39:52 +00:00
Subrata Banik 45df1066ef mb/google/rex: Mark unused USB ports as empty
This patch marks unused USB ports (USB2.0/TCSS) empty to avoid
prompting wrong dmesg as below.

   ```
  usb usb2-port3: Cannot enable. Maybe the USB cable is bad?
   ```
Mainboard variants to override the USB ports as per the target
board design.

TEST=Able to build and boot google/rex with all USB ports are
working as expected.

Change-Id: Ic3d21151a22f2318413f480f3386bf2dbf696307
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73027
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-16 00:39:26 +00:00
Zoey Wu 57987b6e19 mb/google/brask/var/aurash: Initiate coreboot setting
Initial Aurash configuration base on moli design.

1. Set up gpio.
2. Add memory config.
3. There is no SD card setting on aurash, remove it from overridetree.
4. Follow moli psys schematic design.
5. Enable BT offload.

BUG=b:269063331
TEST=emerge-brask coreboot.

Signed-off-by: Zoey Wu <zoey_wu@wistron.corp-partner.google.com>
Change-Id: Ia9088cc2937bab72c8c22af592392384a10616a4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73013
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ricky Chang <rickytlchang@google.com>
2023-02-16 00:37:53 +00:00
Johnny Lin 107e7aa0f5 cpu/x86/smm: Enable setting SMM console log level from mainboard
Add a Kconfig RUNTIME_CONFIGURABLE_SMM_LOGLEVEL that enables
mainboard to override mainboard_set_smm_log_level for SMM log level.
This can let SMM have different log level than other stages for
more flexibility.

Another reason is that getting certain data that requires searching
from flash VPD or CMOS is not very ideal to be done in SMM, so in this
change the value can be passed via the member variable in struct
smm_runtime and be referenced directly in SMM.

One example is that mainboard can get the desired SMM log level from
VPD/CMOS, and pass SMM console log level via the variable and in SMM
it can be referenced in get_console_loglevel() override function
directly.

Tested=On OCP Delta Lake, verified SMM log level can be overridden.

Change-Id: I81722a4f1bf75ec942cc06e403ad702dfe938e71
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49460
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2023-02-15 21:53:07 +00:00
Anil Kumar e822fb3587 soc/intel/alderlake: Disable package C-state demotion for Raptor Lake
While executing S0ix tests on Raptor Lake boards, we observed CPU fails
to enter suspend state, causing failure.

As a workaround, disable package C-state demotion, till this issue
is fixed in ucode.

BUG=268296760
BRANCH=firmware-brya-14505.B
TEST=Boot and verified that S0ix issue is resolved.

Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Change-Id: Ie50e1024f4118d82d2ad762b54fa722c43990d12
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72942
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-02-15 17:57:41 +00:00
Felix Singer ab0a19c9e6 mb/hp/snb_ivb_laptops: Clean up USBDEBUG_HCD_INDEX setting
Change-Id: Iab21376d1887b0c79ea463885520781d042b040d
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73035
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-02-15 17:30:28 +00:00
Michał Żygowski 23b7948355 pc80/i8254: Add speaker beep function
Some platforms have an onboard speaker which could be used as an
indicator of successful boot or critical error, e.g. in die_notify
function. The function assumes that SPKR GPIO is properly configured
by the platform code.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I8189b3462bb5140af352fa786db3a6a2a45076f2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68100
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2023-02-15 13:17:29 +00:00
Lean Sheng Tan 53ee1bba72 soc/intel/adl: Correct wrongly reported ADL PCH SKU
Per Intel 600 & 700 series PCH EDS (626817), these PCH IDs belongs
to ADL not RPL, though some RPL SoCs are also using ADL PCH.
Hence correct the name reporting to avoid confusion when ADL SoCs
were used.

Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I61a608e2c99b1d60a99d6ad734b396676f3a2ab2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72999
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-15 13:16:36 +00:00
Jamie Chen 135ac25faf mb/google/brya/var/omnigul: Add memory parts support
Add new memory parts in the mem_parts_used.txt and generate the
SPD ID for the parts. The memory parts being added are:

1) Samsung K3KL8L80CM-MGCT
2) Hynix H58G56BK7BX068
3) Micron MT62F1G32D2DS-026 WT:B
4) Micron MT62F512M32D2DR-031 WT:B
5) Hynix H58G56BK8BX068

BUG=b:264340545
BRANCH=firmware-brya-14505.B
TEST=FW_NAME=omnigul emerge-brya coreboot

Change-Id: I1f650c7e90804e871572f42ac925da85afd7f9d3
Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72886
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyle Lin <kylelinck@google.com>
2023-02-15 13:15:52 +00:00
Usha P c6b406e8c6 mb/intel/mtlrvp: Enable mipi_camera for MTL-P RVP
Add support for MTL-P RVP mipi camera functionality

BUG=None
TEST=Build and boot MTL-P RVP to Chrome OS. Verify SSDT entries
related to mipi camera and verify camera working.

Scope (\_SB.PCI0.I2C1)
{
    Device (CAM0)

Scope (\_SB.PCI0.I2C0)
{
    Device (CAM1)

Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: I698edd7155fc38477f3416900799e61d3295fd1a
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73016
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Harsha B R <harsha.b.r@intel.com>
2023-02-15 13:15:20 +00:00
Usha P 65654339f9 mb/intel/mtlrvp: Enable Audio for MTL-P RVP
This patch adds FW_CONFIG and codec support for MTL-P RVP

BUG=None
TEST=Build and boot MTL-P RVP to Chrome OS. Verify audio codec listed
under aplay -l and audio working with the connected audio card.

localhost ~ # aplay -l
**** List of PLAYBACK Hardware Devices ****
card 0: sofrt5682 [sof-rt5682], device 0: Headset (*) []
  Subdevices: 1/1
  Subdevice #0: subdevice #0
card 0: sofrt5682 [sof-rt5682], device 1: Speakers (*) []
  Subdevices: 1/1
  Subdevice #0: subdevice #0
card 0: sofrt5682 [sof-rt5682], device 5: HDMI1 (*) []
  Subdevices: 1/1
  Subdevice #0: subdevice #0
card 0: sofrt5682 [sof-rt5682], device 6: HDMI2 (*) []
  Subdevices: 1/1
  Subdevice #0: subdevice #0
card 0: sofrt5682 [sof-rt5682], device 7: HDMI3 (*) []
  Subdevices: 1/1
  Subdevice #0: subdevice #0
card 0: sofrt5682 [sof-rt5682], device 8: HDMI4 (*) []
  Subdevices: 1/1
  Subdevice #0: subdevice #0

Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: Ib29ac3e4105e578e1555076d180b35a8265a99c8
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73015
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-15 13:14:26 +00:00
Jamie Chen 47f84d3a24 spd/lp5: Add new part H58G56BK8BX068
HYNIX H58G56BK8BX068 will be used for omnigul.
Add it to the parts list and regenerate the SPDs using spd_gen.

BUG=b:264340545
TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5

Change-Id: Id4adbaf7611e34107522df988482d9efd229d514
Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72967
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-02-15 13:10:55 +00:00
Felix Singer e31c0f00fa mb/asrock/b75pro3-m: Reorder Kconfig selects alphabetically
Built asrock/b75pro3-m with BUILD_TIMELESS=1 and coreboot.rom remains
the same.

Change-Id: I8db6b870f2d4aac35766717866b519921d270f9e
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73030
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-02-15 13:10:01 +00:00
Martin Roth 60f367a473 util/release: Update build-release script
- Make variables for the release name and the tarballs instead of
writing them out every time.
- Skip some more unnecessary files when creating the tarballs.
- Remove unnecessary check for the commit ID. It's now a required field.
- Correctly get and save the time of the last release for use in
creating the tarballs.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I56cd5e2dcf01ee55e5d45e837db2f89904b06ddd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73004
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-02-15 13:08:45 +00:00
Fred Reitberger 09718f3cf3 mb/amd/chausie,mayan: Use common missing APCB warning
Use the common missing APCB warning when the APCB is missing

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Ie6303bc3457731bcac322770c4c08712f89fce3a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73003
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-02-15 13:07:56 +00:00
Fred Reitberger a63fac3c58 soc/amd/common: Move missing APCB warning to common area
Move missing APCB warning from birman to amd/common so that other
mainboards can utilize the same warnings if the APCB is missing.

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I7ae689726ae4f7ccdf6959e47cbb5aee15cdb690
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73002
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-02-15 13:07:04 +00:00
Fred Reitberger e814b265ea soc/amd/common/Makefile.inc: Extend if case coverage
Extend the coverage of the 'ifeq ($(CONFIG_SOC_AMD_COMMON),y)' case to
the entire file. This matches the coverage of the related Kconfig.

Add comments to endif to show which if they are ending.

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I369e23e7ee9463ca1ae487d1e2181c760ae1bab2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70208
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-02-15 13:06:28 +00:00
Morris Hsu 87577169e3 mb/google/brask/var/constitution: update gpio settings
Configure GPIOs according to schematics

TEST=emerge-brask coreboot

Change-Id: Ib27f1c334cad47b3be57f57b7cc8ca5530118328
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72945
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-15 03:07:19 +00:00
Tarun Tuli 2072296330 mb/google/brya/agah: Adjust i2c1 and i2c2 timing Parameters for 400KHz
Adjust timing parameters on i2c1 and i2c2 to meet timing requirements.

For SCL, the t-high time is now over the min 600ns requirement
for 400KHz operation (measure at over 700ns). Also, this change
does not violate other parameters - rise time, setup time and hold time.

BUG=b:264704732
TEST=Verified all timings meet spec now

Change-Id: I0e92b2c9c25e7fb5fa7082af3f4a88da168c3ef2
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-15 02:14:15 +00:00
Tarun Tuli 944aff2635 mb/google/brya/acpi: Update checksum in NVPCF DSM subfunction
The NVPCF DSM subfunction specified a incorrect checksum.
Update this function to the proper checksum of 0xaf.

BUG=b:214581372
TEST=build

Change-Id: Ib58bd6cc10703ca67a7a4f520273865a95a4702b
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-15 02:13:31 +00:00
Usha P df6bc335f5 mb/intel/mtlrvp: Enable S0ix
This patch enables S0ix for MTL-P RVP platform

BUG=None
TEST=Able to enter low power idle S0 on MTL-P RVP

Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: Id84f21d81197e44d6dd0dd8888c80848aa3679e0
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71994
Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Harsha B R <harsha.b.r@intel.com>
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
2023-02-15 02:10:12 +00:00
Shon Wang f8665f08fa Revert "mb/google/brya/vell: Add PS1/PS2 cutoff point"
This reverts commit e30695dbe1.

for meet thermal criteria, modify PS1/PS2 cutoff to default value

BUG=b:229803757
BRANCH=brya
TEST='FW_NAME=vell emerge-brya coreboot'

Change-Id: Ie009788116f1e25db8aed2df58102a316a8aeef2
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72833
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-15 02:07:58 +00:00
Zoey Wu c9dff8b0c2 mb/google/brya: Add Kconfig for TPM I2C bus
Add TPM I2C for aurash to avoid TPM I2C fail.

BUG=b:269050049
TEST=emerge-brask coreboot.

Signed-off-by: Zoey Wu <zoey_wu@wistron.corp-partner.google.com>
Change-Id: I1947d2e1189f46d8dab01837f75de7cb6e9e0579
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73011
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-15 00:30:40 +00:00
Zheng Bao 4bfb36ed68 amdfwtool: use SoC ID info instead of misleading comboable flag
Since it actually depends on the SoC type whether the old PSP
directory table pointer or the new comboable PSP directory table
pointer is used in EFS, get this information from the SoC ID instead
of passing the comboable flag for the SoCs that need to use the new
comboable PSP directory table pointer.

TEST=Binary identical on amd/majolica, pcengines/apu2, amd/gardenia

Change-Id: I0c3f21065939d1b13c2607aba16cbef74dd8d389
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73020
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-02-14 18:24:08 +00:00
Isaac Lee af69de494e mb/google/skyrim: Create whiterun variant
Create the whiterun variant of the skyrim reference board by
copying the winterhold files to a new directory named for the variant.

BUG=b:265955979
BRANCH=None
TEST=emerge-skyrim coreboot and boot up on Whiterun

Change-Id: I3539f84e79c05936fe006bfe9d08743d6a9a6ba7
Signed-off-by: Isaac Lee <isaaclee@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72483
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-14 18:04:39 +00:00
Matt DeVillier 728cf8a830 mb/google/skyrim: Add support for and select USE_SELECTIVE_GOP_INIT
Add a FMAP region to support caching GOP-driver-modified VBIOS tables.
Select SOC_AMD_GFX_CACHE_VBIOS_IN_FMAP if CHROMEOS && RUN_FSP_GOP.
Default USE_SELECTIVE_GOP_INIT to y if CHROMEOS && RUN_FSP_GOP.

BUG=b:255812886
TEST=build/boot skyrim, verify cached VBIOS data differs from VBIOS
in CBFS, cached VBIOS data is used when not booting in recovery
or developer modes.

Change-Id: I5857fa4a15250bf6478bffa96b16200e318492b1
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-02-14 18:03:59 +00:00
Matt DeVillier 7404d21cf8 mb/google/hatch: drop include for puff baseboard
Commit 45b1da33c8 ("mb/google/hatch: split up hatch and puff
baseboards") moved puff out from under hatch into its own
mainboard dir, but this basebaord include was left behind.
Delete it as it's not needed.

TEST=build hatch variants

Change-Id: I9045c52006fd232552541d68972d831c8b52da27
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73000
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-14 11:39:45 +00:00
Matt DeVillier b7f032d3c9 drivers/i2c/nau8825: Fix typo: deboune -> debounce
Allows Windows/Linux driver to use the proper jack eject debounce time.
Credit to coolstar for identifying the issue.

Change-Id: I32b94b9285f7c85ff1d67b3d78c845835bbf90d7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73001
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-14 11:39:08 +00:00
Patrick Rudolph 88e5d18589 soc/intel/alderlake: Add missing SATA DSDT device
Add "SATA" to DSDT as it's referenced by Intel PEP SSDT.

Fixes warning shown in Linux:
  ACPI Error: AE_NOT_FOUND, While resolving a named reference
  package element - \_SB_.PCI0.SATA (20220331/dspkginit-438)

Change-Id: I65a1d17bce246022859f011cdc4712e1206a98fe
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72762
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-02-14 07:48:33 +00:00
CoolStar e145c2fbe2 acpi/acpigen_dptf: Add pkg return to dptf_write_power_limits()
The PPCC method should return the package, but is missing the return
statement, leading to DPTF/S0ix to not function properly. Add the
required return statement.

TEST=build/boot Win11 on google/banshee, verify DPTF, S0ix functional.

Change-Id: I051db7d69dd6cdfbb07caf649247ee166c1c74ac
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72921
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-02-14 05:39:57 +00:00
Subrata Banik 487cd399df mb/google/rex: Set `SkipExtGfxScan` FSP-M UPD
This patch overrides `SkipExtGfxScan` UPD as the Rex device is
equipped with an on-board graphics device hence, skip scanning
external GFX devices.

BUG=b:228002764
TEST=Able to save ~1ms+ boot time on google/rex.

FSP FPDT Data is showing the timestamp between those function calls.

Without this patch:
[INFO ] CheckOffboardPcieVga/5b7cc220-e183-481c-87f427a92d8db88f -> 979684 -> 22
[INFO ] CheckOffboardPcieVga/5b7cc220-e183-481c-87f427a92d8db88f -> 980815 -> 1131

With this patch:

`CheckOffboardPcieVga` is not getting called.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I20aa09e80671ab94e639787f40b95b740bbe5efb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72948
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-02-14 02:58:36 +00:00
Subrata Banik f57eb1a640 soc/intel/meteorlake: Hook up `SkipExtGfxScan` FSP-M UPD
This patch allows override to the `SkipExtGfxScan` UPD.
Ideally a platform with an on-board graphics device should skip
scanning external GFX devices aka set this UPD to `1`.

BUG=b:228002764
TEST=Able to build and boot google/rex.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I00e15b71ed67119df9ca6f98a750ede109ff33fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72947
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-02-14 02:58:24 +00:00
John Su cad99d8c17 mb/google/skyrim/var/frostflow: Update Package Power Parameters
Follow thermal table to modify setting.
"stapm_time_constant_s" = "200" to "275"

BRANCH=none
BUG=b:257149501
TEST=emerge-skyrim coreboot

Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I7fe05fe1c17258a3323b8d04302212e76a388797
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72934
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2023-02-13 17:03:51 +00:00
Matt DeVillier bcb67ed3c5 soc/amd/mendocino: Add support for selective GOP driver init
Add support for the selective GOP init feature by only running the FSP
GOP driver when necessary: if the FMAP cache is invalid, or if the
board is booted in either recovery or developer mode.

BUG=b:255812886
TEST=tested with rest of patch train

Change-Id: I7ddadc254e05aca0fdd7a9567160a9329cb0e15c
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70899
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-02-13 14:57:31 +00:00