Commit graph

19 commits

Author SHA1 Message Date
Jonathan Neuschäfer
c5ebb1d005 riscv: Move mcall numbers to mcall.h, adjust their names
The new name and location make more sense:

 - The instruction used to call into machine mode isn't called "ecall"
   anymore; it's mcall now.
 - Having SBI_ in the name is slightly wrong, too: these numbers are not
   part of the Supervisor Binary Interface, they are just used to
   forward SBI calls (they could be renumbered arbitrarily without
   breaking an OS that's run under coreboot).

Also remove mcall_dev_{req,resp} and the corresponding mcall numbers,
which are no longer used.

Change-Id: I76a8cb04e4ace51964b1cb4f67d49cfee9850da7
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/18146
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-01-16 06:15:53 +01:00
Ronald G. Minnich
6f3a53b6f6 riscv: get SBI calls to work
SBI calls, as it turned out, were never right.
They did not set the stack correctly on traps.
They were not correctly setting the MIP instead of the SIP
(although this was not really well documented).
On Harvey, we were trying to avoid using them,
and due to a bug in SPIKE, our avoidance worked.
Once SPIKE was fixed, our avoidance broke.

This set of changes is tested and working with Harvey
which, for the first time, is making SBI calls.

It's not pretty and we're going to want to rework
trap_util.S in coming days.

Change-Id: Ibef530adcc58d33e2c44ff758e0b7d2acbdc5e99
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/18097
Tested-by: build bot (Jenkins)
2017-01-16 00:26:08 +01:00
Ronald G. Minnich
d9307c2e8a riscv: Add support for timer interrupts
RISCV requires that timer interrupts be handled in machine
mode and delegated as necessary. Also you can only reset the
timer interrupt by writing to mtimecmp. Further, you must
write a number > mtime, not just != mtime. This rather clumsy
situation requires that we write some value into the future
into mtimecmp lest we never be able to leave machine mode as
the interrupt either is not cleared or instantly reoccurs.

This current code is tested and works for harvey (Plan 9)
timer interrupts.

Change-Id: I8538d5fd8d80d9347773c638f5cbf0da18dc1cae
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/17807
Tested-by: build bot (Jenkins)
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2016-12-18 07:09:19 +01:00
Jonathan Neuschäfer
99f2f113ec riscv: Unify SBI call implementations under arch/riscv/
Note that currently, traps are only handled by the trap handler
installed in the bootblock. The romstage and ramstage don't override it.

TEST=Booted emulation/spike-qemu and lowrisc/nexys4ddr with a linux
     payload. It worked as much as before (Linux didn't boot, but it
     made some successful SBI calls)

Change-Id: Icce96ab3f41ae0f34bd86e30f9ff17c30317854e
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/17057
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-11-07 16:47:49 +01:00
Ronald G. Minnich
571c230252 riscv: Add a bandaid for the new toolchain
After I did a new toolchain build, I found the
the mhartid register value is wrong for Spike.
The docs seem to agree with Spike, not the
code the toolchain produces?

Until such time as the bitstreams and toolchain can find
a way to agree, just hardcode it. We've been playing this game
for two years now so this is hardly a new approach.

This is intentionally ugly because we really need the
toolchains and emulators and bitstreams to sync up,
and that's not happening yet. Lowrisc
allegedly implements the v1.9 spec but it's PTEs are clearly
1.7. Once it all settles down we can just use constants
supplied by the toolchain.

I hope the syncup will have happened by the workshop in November.

This gets spike running again.

Change-Id: If259bcb6b6320ef01ed29a20ce3d2dcfd0bc7326
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/17183
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2016-11-02 19:01:42 +01:00
Jonathan Neuschäfer
0bc12abc2b arch/riscv: In trap handler, don't print SP twice
The stack pointer (SP) is already printed in print_trap_information.
Don't print it again in handle_misaligned_{load,store}.

Change-Id: I156cf5734a16605decc2280e54e6db3089e094a2
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/16996
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-18 18:42:11 +02:00
Jonathan Neuschäfer
2f72a618f1 arch/riscv: Visually align trap frame information
The pointers printed on unaligned memory accesses are now aligned to
those printed at the end of print_trap_information.

Change-Id: Ifec1cb639036ce61b81fe8d0a9b14c00d5b2781a
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/16983
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-10-15 00:28:14 +02:00
Jonathan Neuschäfer
2af174a7dc riscv and power8: Convert printk/while(1) to die
Change-Id: I277cc9ae22cd33f2cd9ded808960349d09e8670d
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/16984
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-10-15 00:24:46 +02:00
Jonathan Neuschäfer
a1e3924869 arch/riscv: Add missing "break;"
Change-Id: Iea3f12a5a7eb37586f5424db2d7a84c4319492f8
Reported-by: Coverity (1361947)
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/16335
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-29 18:01:27 +02:00
Jonathan Neuschäfer
857e33e27f arch/riscv: Implement the SBI again
Not all SBI calls are implemented, but it's enough to see a couple dozen
lines of Linux boot output.

It should also be noted that the SBI is still in flux:
https://groups.google.com/a/groups.riscv.org/forum/#!topic/sw-dev/6oNhlW0OFKM

Change-Id: I80e4fe508336d6428ca7136bc388fbc3cda4f1e4
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/16119
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-08-23 23:47:01 +02:00
Jonathan Neuschäfer
b6648cd888 arch/riscv: Fix unaligned memory access emulation
Change-Id: I06c6493355f25f3780f75e345c517b434912696f
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/16261
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-08-23 23:43:24 +02:00
Jonathan Neuschäfer
363526cfb8 arch/riscv: Improve and refactor trap handling diagnostics
Change-Id: I57032f958c88ea83a420e93b459df4f620799d84
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/16016
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-08-15 18:28:03 +02:00
Jonathan Neuschäfer
1b1d4b7ae6 arch/riscv: Enable unaligned load handling
Change-Id: If1c63971335a6e2963e01352acfa4bd0c1d86bc2
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/15590
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-19 20:22:25 +02:00
Jonathan Neuschäfer
fefc77afd0 arch/riscv: Show fault PC and load address on load access faults
Change-Id: Ib0535bf25ce25550cc17f64177f804a70aa13fb3
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/15286
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-06-28 18:53:04 +02:00
Andrew Waterman
38cd3756b8 RISC-V: Add more debug info to debug printks
Change-Id: I49292e69a5636c675bb8ed7cfe4462ca8189487e
Signed-off-by: Andrew Waterman <waterman@cs.berkeley.edu>
Reviewed-on: https://review.coreboot.org/13736
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2016-02-19 05:42:52 +01:00
Andrew Waterman
f16d904192 RISC-V: Make inline asm usage safer
Change-Id: Id547c98e876e9fd64fa4d12239a2608bfd2495d2
Signed-off-by: Andrew Waterman <aswaterman@gmail.com>
Reviewed-on: https://review.coreboot.org/13735
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2016-02-19 05:42:32 +01:00
Patrick Georgi
a73b93157f tree: drop last paragraph of GPL copyright header
It encourages users from writing to the FSF without giving an address.
Linux also prefers to drop that and their checkpatch.pl (that we
imported) looks out for that.

This is the result of util/scripts/no-fsf-addresses.sh with no further
editing.

Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/11888
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-31 21:37:39 +01:00
Thaminda Edirisooriya
d9653e1328 riscv-trap-handling: Add functionality, prevent stack corruption
Trap handling code was bugged in that it loaded in the wrong stack
pointer, overwriting the space the processor uses to talk to its host
for doing device requests. Fix this issue, as well as add support for
handling misaligned loads the same way we handle misaligned stores.

Change-Id: I68ba3a114b7167b3212bb0bed181a7595f0b97d8
Signed-off-by: Thaminda Edirisooriya <thaminda@google.com>
Reviewed-on: http://review.coreboot.org/11620
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-09-15 18:04:37 +00:00
Thaminda Edirisooriya
95ba4c87f5 riscv-trap-handling: Add implementation for trap calls in riscv
RISCV requires the bios/bootloader to set up an interface by which it
can get information about memory, talk to host devices, etc. Put
implementation for spike in
src/mainboard/emulation/spike-riscv/spike_util.c, and
src/arch/riscv/trap_handler.c

Change-Id: Ie1d5f361595e48fa6cc1fac25485ad623ecdc717
Signed-off-by: Thaminda Edirisooriya <thaminda@google.com>
Reviewed-on: http://review.coreboot.org/11368
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-09-10 17:26:38 +00:00