We have the git history which is a more reliable librarian.
Change-Id: Idbcc5ceeb33804204e56d62491cb58146f7c9f37
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
This GPIO dumping was implemented using the
Document Number: 341080-001
Intel® 495 Series Chipset Family On-Package Platform Controller Hub
Volume 1 of 2
datasheet. The GPIO community ports can be found in table 36-1, while
the community and pin descriptions are taken from
linux/pinctrl/intel/pinctrl-icelake.c .
This commit was tested on the late 2019 Razer Blade Stealth with 1065G7
and Chipset 495 PCH and the output manually compared against
linux/pinctrl-intel.
Change-Id: Ib40f1dbae57169678e92ea9ad0df60ff91b5b22c
Signed-off-by: Johanna Schander <coreboot@mimoja.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Sunrise Point-LP is used on Skylake and KabyLake platforms,
but the PCH IDs differ.
This commit adds the PCH IDs for Skylake mobile platforms
and renames the Kabylake macros to distinguish them.
Used Intel documents:
- 332995-001EN (I/O datasheet vol. 1)
- 332996-002EN (I/O datasheet vol. 2)
Change-Id: Id46224fcc44b06c91cbcd6c74a55c95e1de65ec6
Signed-off-by: Felix Singer <migy@darmstadt.ccc.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31506
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Values from
- Intel doc 337347 rev4
- coreboot soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h
On Coffeelake H (using Cannonlake / Cannonpoint PCH) p2sb is not
accessible. Using a static value instead. 0xfd000000 is a common value
chosen by coreboot and non-coreboot firmware.
Change-Id: Id637f703ab0a99eb0908ecdc3da27ba80db1c6b8
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31500
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Fixes getting a dump of GPIO registers for these devices.
Change-Id: I80f05a170152969ba45d6aee33ab7ed5296ee496
Signed-off-by: Shaleen Jain <shaleen@jain.sh>
Reviewed-on: https://review.coreboot.org/c/30604
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The P2SB (PCI to Side-Band) bridge is on a different PCI device on APL.
Hence, we have to decide based on the LPC ID which device to query.
Also fix a comment.
Change-Id: Ie20d7d2d246629d085bcf4740ba28b1e81e6a12a
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/29896
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
SoCs from Skylake on have many settings as so called private con-
figuration registers (PCRs). These are organized as 256 ports with
a 64KiB space each. We use the Primary to Sideband (P2SB) bridge's
BAR to access them.
Change-Id: Iede4ac601355e2be377bc986d62d20098980ec35
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/19593
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Primary to Sideband Bridge (P2SB) is the interface to Private Con-
figuration Registers (PCR) including GPIO configuration. Of course,
access is restricted to Intel partners and criminals, so the PCI device
is hidden from the OS. Probably we only need to fetch the SBREG_BAR
address and can hide the PCI device again after that.
Change-Id: Ic121a09f021708aab82ae4b9d76d6c3c6fb884fa
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/19588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Patrick Georgi