Commit graph

15 commits

Author SHA1 Message Date
Angel Pons
df7a887cb5 sb/intel/lynxpoint: Align LP GPIO ACPI with Broadwell
Move the `GWAK` method into the GPIO device, and have lpc.c include the
LP GPIO code. All usages of `GWAK` on mainboards need to be updated.

Change-Id: Id6a41f553d133f960de8b232205ed43b832a83d2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46775
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-04 23:21:44 +00:00
Elyes HAOUAS
3ed5c9e3cd mb/google/beltino: Convert to ASL 2.0 syntax
Built google/beltino (Monroe) provides identical 'dsdt.dsl'.

Change-Id: I12b6a8264e53ece30ae79da2d79c6f1d302fb357
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46170
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-11-04 09:43:09 +00:00
Patrick Georgi
6b5bc77c9b treewide: Remove "this file is part of" lines
Stefan thinks they don't add value.

Command used:
sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool)

The exceptions are for:
 - crossgcc (patch file)
 - gcov (imported from gcc)
 - elf.h (imported from GNU's libc)
 - nvramtool (more complicated header)

The removed lines are:
-       fmt.Fprintln(f, "/* This file is part of the coreboot project. */")
-# This file is part of a set of unofficial pre-commit hooks available
-/* This file is part of coreboot */
-# This file is part of msrtool.
-/* This file is part of msrtool. */
- * This file is part of ncurses, designed to be appended after curses.h.in
-/* This file is part of pgtblgen. */
- * This file is part of the coreboot project.
- /* This file is part of the coreboot project. */
-#  This file is part of the coreboot project.
-# This file is part of the coreboot project.
-## This file is part of the coreboot project.
--- This file is part of the coreboot project.
-/* This file is part of the coreboot project */
-/* This file is part of the coreboot project. */
-;## This file is part of the coreboot project.
-# This file is part of the coreboot project. It originated in the
- * This file is part of the coreinfo project.
-## This file is part of the coreinfo project.
- * This file is part of the depthcharge project.
-/* This file is part of the depthcharge project. */
-/* This file is part of the ectool project. */
- * This file is part of the GNU C Library.
- * This file is part of the libpayload project.
-## This file is part of the libpayload project.
-/* This file is part of the Linux kernel. */
-## This file is part of the superiotool project.
-/* This file is part of the superiotool project */
-/* This file is part of uio_usbdebug */

Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11 17:11:40 +00:00
Angel Pons
64b5d974d5 mb/google/beltino: Use SPDX for GPL-2.0-only files
Done with sed and God Lines. Only done for C-like code for now.

Change-Id: Ie7a2074c2319911395234e4ce8ec35b8209bcc01
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40144
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-04-06 13:45:52 +00:00
Patrick Georgi
a2fe7789e9 mainboard/google: Remove copyright notices
They're listed in AUTHORS and often incorrect anyway, for example:
- What's a "Copyright $year-present"?
- Which incarnation of Google (Inc, LLC, ...) is the current
  copyright holder?
- People sometimes have their editor auto-add themselves to files even
  though they only deleted stuff
- Or they let the editor automatically update the copyright year,
  because why not?
- Who is the copyright holder "The coreboot project Authors"?
- Or "Generated Code"?

Sidestep all these issues by simply not putting these notices in
individual files, let's list all copyright holders in AUTHORS instead
and use the git history to deal with the rest.

Change-Id: I09cc279b1f75952bb397de2c3f2b299255163685
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39607
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2020-03-18 16:44:31 +00:00
Arthur Heymans
72c483a95a sb/intel/lynxpoint: Use sb/intel/common/platform.asl
Change-Id: I86260a374a3f60f16dc73573e7989f0a4ffec818
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-04 11:46:42 +00:00
Arthur Heymans
c54d14f5b4 cpu/intel/haswell: Rework acpi/cpu.asl
Use acpigen_write_processor_cnot to implement notifications the CPU.
Generate PPKG in SSDT.

Change-Id: I126989e8737720f55f7ce113ff4e32bfe0f22620
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/29885
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-30 21:52:00 +00:00
Tristan Corrick
32664fd323 sb/intel/lynxpoint: Add a common platform.asl file
The platform.asl file is copied from sb/intel/bd82x6x, and also matches
the contents deleted from each mainboard's platform.asl.

Tested on an ASRock H81M-HDS and a Google Peppy board (variant of
Slippy). No issues arose from this patch.

Change-Id: I539e401ce9af83070f69147526ca3b1c122f042c
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/29386
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-11-01 22:24:03 +00:00
Tristan Corrick
f3127d4af7 sb/intel/lynxpoint: Automatically generate the ACPI PCI routing table
This patch is based on a8a9f34e9b ("sb/intel/i82801{g,j}x:
Automatically generate ACPI PIRQ tables")

Tested on an ASRock H81M-HDS. The generated _PRT object looks correct,
and the system doesn't show any issue when running. The following
assignments occur:

	ACPI_PIRQ_GEN: PCI: 00:02.0: pin=0 pirq=0
	ACPI_PIRQ_GEN: PCI: 00:03.0: pin=0 pirq=0
	ACPI_PIRQ_GEN: PCI: 00:14.0: pin=0 pirq=0
	ACPI_PIRQ_GEN: PCI: 00:16.0: pin=0 pirq=0
	ACPI_PIRQ_GEN: PCI: 00:1a.0: pin=0 pirq=0
	ACPI_PIRQ_GEN: PCI: 00:1b.0: pin=0 pirq=6
	ACPI_PIRQ_GEN: PCI: 00:1c.0: pin=0 pirq=0
	ACPI_PIRQ_GEN: PCI: 00:1c.1: pin=1 pirq=1
	ACPI_PIRQ_GEN: PCI: 00:1c.2: pin=2 pirq=2
	ACPI_PIRQ_GEN: PCI: 00:1c.3: pin=3 pirq=3
	ACPI_PIRQ_GEN: PCI: 00:1d.0: pin=0 pirq=7
	ACPI_PIRQ_GEN: PCI: 00:1f.2: pin=1 pirq=3
	ACPI_PIRQ_GEN: PCI: 00:1f.3: pin=2 pirq=2

Also tested on a Google Peppy board. The following assignments occur:

	ACPI_PIRQ_GEN: PCI: 00:02.0: pin=0 pirq=0
	ACPI_PIRQ_GEN: PCI: 00:03.0: pin=0 pirq=0
	ACPI_PIRQ_GEN: PCI: 00:14.0: pin=0 pirq=2
	ACPI_PIRQ_GEN: PCI: 00:1b.0: pin=0 pirq=6
	ACPI_PIRQ_GEN: PCI: 00:1c.0: pin=0 pirq=0
	ACPI_PIRQ_GEN: PCI: 00:1d.0: pin=0 pirq=3
	ACPI_PIRQ_GEN: PCI: 00:1f.2: pin=0 pirq=6
	ACPI_PIRQ_GEN: PCI: 00:1f.3: pin=1 pirq=2
	ACPI_PIRQ_GEN: PCI: 00:1f.6: pin=2 pirq=1

A diff of the _PRT object for the Google Peppy board is below. The code
used in the diff has been modified for clarity, but the semantics remain
the same. To summarise the diff:

* The disabled PCIe root ports are no longer included.

* The LPC controller is no longer included, as it has no interrupt pin.
  The pins for the remaining LPC devices are each one less. Perhaps the
  original _PRT object was incorrect?

* The SDIO device is no longer included, as it is disabled.

* The Serial IO devices are no longer included, but that is due to a
  separate issue I am having with this system (the devices don't show up
  under Linux regardless of this patch). In short: their omission is not
  a fault of this patch.

--- pre/_PRT
+++ post/_PRT
@@ -1,301 +1,157 @@
         Method (_PRT, 0, NotSerialized)  // _PRT: PCI Routing Table
         {
             If (PICM)
             {
-                Return (Package (0x12)
+                Return (Package (0x09)
                 {
                     Package (0x04)
                     {
                         0x0002FFFF,
                         Zero,
                         Zero,
                         0x10
                     },

                     Package (0x04)
                     {
                         0x0003FFFF,
                         Zero,
                         Zero,
                         0x10
                     },

                     Package (0x04)
                     {
                         0x0014FFFF,
                         Zero,
                         Zero,
                         0x12
                     },

                     Package (0x04)
                     {
                         0x001BFFFF,
                         Zero,
                         Zero,
                         0x16
                     },

                     Package (0x04)
                     {
                         0x001CFFFF,
                         Zero,
                         Zero,
                         0x10
                     },

-                    Package (0x04)
-                    {
-                        0x001CFFFF,
-                        One,
-                        Zero,
-                        0x11
-                    },
-
-                    Package (0x04)
-                    {
-                        0x001CFFFF,
-                        0x02,
-                        Zero,
-                        0x12
-                    },
-
-                    Package (0x04)
-                    {
-                        0x001CFFFF,
-                        0x03,
-                        Zero,
-                        0x13
-                    },
-
                     Package (0x04)
                     {
                         0x001DFFFF,
                         Zero,
                         Zero,
                         0x13
                     },

                     Package (0x04)
                     {
                         0x001FFFFF,
                         Zero,
                         Zero,
                         0x16
                     },

                     Package (0x04)
                     {
                         0x001FFFFF,
                         One,
                         Zero,
                         0x12
                     },

                     Package (0x04)
                     {
                         0x001FFFFF,
                         0x02,
                         Zero,
                         0x11
-                    },
-
-                    Package (0x04)
-                    {
-                        0x001FFFFF,
-                        0x03,
-                        Zero,
-                        0x10
-                    },
-
-                    Package (0x04)
-                    {
-                        0x0015FFFF,
-                        Zero,
-                        Zero,
-                        0x14
-                    },
-
-                    Package (0x04)
-                    {
-                        0x0015FFFF,
-                        One,
-                        Zero,
-                        0x15
-                    },
-
-                    Package (0x04)
-                    {
-                        0x0015FFFF,
-                        0x02,
-                        Zero,
-                        0x15
-                    },
-
-                    Package (0x04)
-                    {
-                        0x0015FFFF,
-                        0x03,
-                        Zero,
-                        0x15
-                    },
-
-                    Package (0x04)
-                    {
-                        0x0017FFFF,
-                        Zero,
-                        Zero,
-                        0x17
                     }
                 })
             }
             Else
             {
-                Return (Package (0x12)
+                Return (Package (0x09)
                 {
                     Package (0x04)
                     {
                         0x0002FFFF,
                         Zero,
                         ^LPCB.LNKA,
                         Zero
                     },

                     Package (0x04)
                     {
                         0x0003FFFF,
                         Zero,
                         ^LPCB.LNKA,
                         Zero
                     },

                     Package (0x04)
                     {
                         0x0014FFFF,
                         Zero,
                         ^LPCB.LNKC,
                         Zero
                     },

                     Package (0x04)
                     {
                         0x001BFFFF,
                         Zero,
                         ^LPCB.LNKG,
                         Zero
                     },

                     Package (0x04)
                     {
                         0x001CFFFF,
                         Zero,
                         ^LPCB.LNKA,
                         Zero
                     },

-                    Package (0x04)
-                    {
-                        0x001CFFFF,
-                        One,
-                        ^LPCB.LNKB,
-                        Zero
-                    },
-
-                    Package (0x04)
-                    {
-                        0x001CFFFF,
-                        0x02,
-                        ^LPCB.LNKC,
-                        Zero
-                    },
-
-                    Package (0x04)
-                    {
-                        0x001CFFFF,
-                        0x03,
-                        ^LPCB.LNKD,
-                        Zero
-                    },
-
                     Package (0x04)
                     {
                         0x001DFFFF,
                         Zero,
                         ^LPCB.LNKD,
                         Zero
                     },

                     Package (0x04)
                     {
                         0x001FFFFF,
                         Zero,
                         ^LPCB.LNKG,
                         Zero
                     },

                     Package (0x04)
                     {
                         0x001FFFFF,
                         One,
                         ^LPCB.LNKC,
                         Zero
                     },

                     Package (0x04)
                     {
                         0x001FFFFF,
                         0x02,
                         ^LPCB.LNKB,
                         Zero
-                    },
-
-                    Package (0x04)
-                    {
-                        0x001FFFFF,
-                        0x03,
-                        ^LPCB.LNKA,
-                        Zero
-                    },
-
-                    Package (0x04)
-                    {
-                        0x0015FFFF,
-                        Zero,
-                        ^LPCB.LNKE,
-                        Zero
-                    },
-
-                    Package (0x04)
-                    {
-                        0x0015FFFF,
-                        One,
-                        ^LPCB.LNKF,
-                        Zero
-                    },
-
-                    Package (0x04)
-                    {
-                        0x0015FFFF,
-                        0x02,
-                        ^LPCB.LNKF,
-                        Zero
-                    },
-
-                    Package (0x04)
-                    {
-                        0x0015FFFF,
-                        0x03,
-                        ^LPCB.LNKF,
-                        Zero
-                    },
-
-                    Package (0x04)
-                    {
-                        0x0017FFFF,
-                        Zero,
-                        ^LPCB.LNKH,
-                        Zero
                     }
                 })
             }
         }

Change-Id: Id3f067cbf7c7d649fbbf774648d8ff928cb752a4
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/29381
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-11-01 22:22:12 +00:00
Elyes HAOUAS
2c5652d72b mb: Fix non-local header treated as local
Change-Id: Ib39305effdb00e032ca07e6d0e0d84cdf3dcf916
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29098
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-10-18 12:51:50 +00:00
Furquan Shaikh
d7b88dcbcd mb/google/x86-boards: Get rid of power button device in coreboot
As per the ACPI specification, there are two types of power button
devices:
1. Fixed hardware power button
2. Generic hardware power button

Fixed hardware power button is added by the OSPM if POWER_BUTTON flag
is not set in FADT by the BIOS. This device has its programming model
in PM1x_EVT_BLK. All ACPI compliant OSes are expected to add this
power button device by default if the power button FADT flag is not
set.

On the other hand, generic hardware power button can be used by
platforms if fixed register space cannot be used for the power button
device. In order to support this, power button device object with HID
PNP0C0C is expected to be added to ACPI tables. Additionally,
POWER_BUTTON flag should be set to indicate the presence of control
method for power button.

Chrome EC mainboards implemented the generic hardware power button in
a broken manner i.e. power button object with HID PNP0C0C is added to
ACPI however none of the boards set POWER_BUTTON flag in FADT. This
results in Linux kernel adding both fixed hardware power button as
well as generic hardware power button to the list of devices present
on the system. Though this is mostly harmless, it is logically
incorrect and can confuse any userspace utilities scanning the ACPI
devices.

This change gets rid of the generic hardware power button from all
google mainboards and relies completely on the fixed hardware power
button.

BUG=b:110913245
TEST=Verified that fixed hardware power button still works correctly
on nautilus.

Change-Id: I733e69affc82ed77aa79c5eca6654aaa531476ca
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-07-25 18:52:40 +00:00
Elyes HAOUAS
808fc8ef87 mb/google: Get rid of whitespace before tab
Change-Id: I24fd33887152c12b9db9742af475115b02b31ff2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26622
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04 09:01:25 +00:00
Martin Roth
a50b1f9dd0 intel bd82x6x/lynxpoint systems: Update ACPI thermal zone handler
Currently the throttle event handler method THRM is defined as an
extern on the intel bd82x6x and lynxpoint chipsets, then defined
again in the platform with thermal event handling.  In newer versions
of IASL, this generates an error, as the method is defined in two
places.  Simply removing the extern causes the call to it to fail on
platforms where it isn't actually defined, so add a preprocessor define
where it's implemented, and only call the method on those platforms.

This also requires moving the thermal handler, which now includes
the define to before the gnvs asl file.

TEST=Build before and after, make sure correct code is included.

Change-Id: I7af4a346496c1352ec20bda8acb338b5d277d99b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26123
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-03 14:19:58 +00:00
Matt DeVillier
1186915c1f google/beltino: add board-specific USB port info
Add capability and location data for USB ports/devices via
_PLD and _UPC ACPI methods, which is utilized by Windows and
required by macOS.

All beltino variants use the exact same USB port layout.

Change-Id: If5b540949ea071f7165876e12ac1ef50e62d2b22
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/19966
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-31 19:10:30 +02:00
Matt DeVillier
81ae67a634 Add Haswell Chromeboxes/Chromebase using variant board scheme
Combine existing board google/panther with new ChromeOS devices
mccloud, monroe, tricky, and zako, using their common reference board
(beltino) as a base.

Chromium sources used:
firmware-mccloud-5827.B 65bfee7 [haswell: No need pre-graphics delay...]
firmware-monroe-4921.B 1ac749d [Monroe: Disable KB/MS in ITE8772.]
firmware-tricky-5829.B 2db5322 [haswell: No need pre-graphics delay...]
firmware-zako-5219.B eacedef [haswell: No need pre-graphics delay...]

Existing google/panther board will be removed in a subsequent commit.

Variant setup modeled after google/reef

Change-Id: I5d7e0c2551e8b0707841032460c35615cefb2886
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/17329
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-24 05:23:36 +01:00