Commit Graph

15062 Commits

Author SHA1 Message Date
David Hendricks 40e89b4e5a edid: Memset output earlier in decode_edid()
This ensures the output buffer is initialized before exiting
decode_edid() so that if the return value is ignored in higher-level
logic (like when dealing with external displays) we don't leave
the struct filled with garbage.

BUG=chrome-os-partner:42946
BRANCH=firmware-veyron
TEST=none

Change-Id: I557e2495157458342db6d8b0b1ecb39f7267f61f
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: bb12dca133576543efa4d3bcc9aadf85d37c8b71
Original-Change-Id: I697436fffadc7dd3af239436061975165a97ec8c
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/293547
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/11389
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-28 06:42:14 +00:00
David Hendricks 7dbf9c6747 edid: Use edid_mode struct to reduce redundancy
This replaces various timing mode parameters parameters with
an edid_mode struct within the edid struct.

BUG=none
BRANCH=firmware-veyron
TEST=built and booted on Mickey, saw display come up, also
compiled for link,falco,peppy,rambi,nyan_big,rush,smaug

[pg: extended to also cover peach_pit, daisy and lenovo/t530]

Change-Id: Icd0d67bfd3c422be087976261806b9525b2b9c7e
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: abcbf25c81b25fadf71cae106e01b3e36391f5e9
Original-Change-Id: I1bfba5b06a708d042286db56b37f67302f61fff6
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/289964
Original-Reviewed-by: Yakir Yang <ykk@rock-chips.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/11388
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-28 06:42:03 +00:00
David Hendricks a3b898aaf0 edid: Clean-up the edid struct
There are serveral members of the edid struct which are never used
outside of the EDID parsing code itself. This patch moves them to a
struct in edid.c. They might be useful some day but until then we can
just pretty print them and not pollute the more general API.

BUG=none
BRANCH=firmware-veyron
TEST=compiled for veyron_mickey, peppy, link, nyan_big, rush, smaug
Signed-off-by: David Hendricks <dhendrix@chromium.org>

Change-Id: I660f28c850163e89fe1f59d6c5cfd6e63a56dda0
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: ee8ea314a0d8f5993508f560fc24ab17604049df
Original-Change-Id: I7fb8674619c0b780cc64f3ab786286225a3fe0e2
Original-Reviewed-on: https://chromium-review.googlesource.com/290333
Original-Reviewed-by: Yakir Yang <ykk@rock-chips.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Queue: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/11387
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-28 06:41:51 +00:00
Douglas Anderson ffe63e2796 veyron: mickey sdram-lpddr3-samsung-2GB.inc now 40 Ohm
The value of 0x4 (60 Ohm) apperas to be causing lots of problems.
Since 0x1 (34.3 Ohm) was _almost_ right, let's try 0x2 (40 Ohm) and
hope it's the sweet spot.

BRANCH=None
BUG=chrome-os-partner:43626
TEST=My mickey now boots up

Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: 06db96e00d39972edbaf8429cbe88bbc66804e15
Original-Change-Id: If8b7d51d058ae000c0af189a648c62fa38a872ac
Original-Signed-off-by: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/291121
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-(cherry picked from commit 0dabadca1ab3bb310f85646d020bdcf672014071)
Original-Reviewed-on: https://chromium-review.googlesource.com/291291

Change-Id: Id32790c894c09616e32503aa790fa294093eca8a
Reviewed-on: http://review.coreboot.org/11386
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-28 06:41:15 +00:00
David Hendricks bf62b8cc8b veyron_rialto: Force 3G modem off
This basically does the same thing for firmware what CL:290631
did in the kernel. We want to keep the modem off until it needs
to be used to avoid enumeration/detection issues.

BUG=chrome-os-partner:43271
BRANCH=none
TEST=needs testing

Change-Id: I3b63a77c732dc4895b728b30f1dd71210a9c0e90
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: a90ccd7fbffe44abe05e96341cc77067442c85e4
Original-Change-Id: I3516de1ea9160f7186ad7f5fb3b5d29ac73143b5
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/290890
Original-Reviewed-by: Alexandru Stan <amstan@chromium.org>
Reviewed-on: http://review.coreboot.org/11385
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-28 06:41:01 +00:00
Tom Warren 50967870a9 T210: Add 128MB VPR allocation/carveout
The NV security team requested that coreboot allocate a 128MB
region in SDRAM for VPR (Video Protection Region). We had
previously just disabled the VPR by setting BOM/SIZE to 0.

Once allocated, the VPR will be locked from further access.
The ALLOW_TZ_WRITE_ACCESS bit is _not_ set, as dynamic VPR config
is not supported at this time (i.e. trusted code can _not_ remap
or resize the VPR).

BUG=None
BRANCH=None
TEST=Built and booted on my P5 A44. Saw the VPR region in the
boot spew (ID:3 [f6800000 - fe800000]). Dumped the MC VideoProtect
registers and verified their values.

Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: a7481dba31dc39f482f8a7bfdaba1d1f4fc3cb81
Original-Change-Id: Ia19af485430bc09dbba28fcef5de16de851f81aa
Original-Signed-off-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/290475
Original-Reviewed-by: Hyung Taek Ryoo <hryoo@nvidia.com>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Hridya Valsaraju <hvalsaraju@nvidia.com>
Original-(cherry picked from commit 9629b318eb17b145315531509f950da02483114f)
Original-Reviewed-on: https://chromium-review.googlesource.com/291095
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>

Change-Id: I19a93c915990644177c491c8212f2cf356d4d17d
Reviewed-on: http://review.coreboot.org/11384
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-28 06:40:43 +00:00
Furquan Shaikh 8b3851969d t210: Move page tables to end of TZDRAM
BL31 makes an assumption that TZDRAM always starts at its base. This
was not true in our case since coreboot page tables were located
towards the start of TZDRAM. Instead move page tables to the end, thus
satisfying the assumption that BL31 base is the base of TZDRAM as
well.

BUG=chrome-os-partner:42989
BRANCH=None
TEST=Compiles successfully and boots to kernel prompt

Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: aabed336da6e9aea426650c5ca5977ccfc83a21b
Original-Change-Id: Ic4d155525dbb4baab95c971f77848e47d5d54dba
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/291020
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-(cherry picked from commit a57127f1655ef311b82c41ce33ffc71db5f9db35)
Original-Reviewed-on: https://chromium-review.googlesource.com/290987

Change-Id: Ie7166fd0301b46eb32f44107f7f782c6d79a278c
Reviewed-on: http://review.coreboot.org/11383
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-28 06:40:32 +00:00
Furquan Shaikh f8142155f9 t210: Pass in required BL31 parameters
BUG=chrome-os-partner:42989
BRANCH=None
TEST=Compiles successfully and boots to kernel prompt.

Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: ff42f0b4e7f81ea97e571ec03adac16b412e4a37
Original-Change-Id: If78857abfb9a348433b8707e58bea1f58416d243
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/291021
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-(cherry picked from commit 68eeb4bb4b817184eb42f4ee3a840317ede07dae)
Original-Reviewed-on: https://chromium-review.googlesource.com/290988
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>

Change-Id: Id555198bc8e5d77f8ceee710d1a432516bd1ae4c
Reviewed-on: http://review.coreboot.org/11382
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-28 06:40:17 +00:00
Tom Warren 0bdb88b106 Smaug: Add NVDEC and TSEC carveouts
The NV security team requested that coreboot allocate the NVDEC
and TSEC carveouts. Added code to set up NVDEC (1 region, 1MB)
and TSEC (2 regions, splitting 2MB), and set their lock bits.
Kernel/trusted code should be able to use the regions now.

Note that this change sets the UNLOCKED bit in Carveout1Cfg0
and Carveout4Cfg0/5Cfg0 (bit 1) to 0 in the BCT .inc files
(both 3GB and 4GB BCTs) so that the BOMs can be written.
Any future revisions to these BCT files should take this
into account.

BUG=None
BRANCH=None
TEST=Built and booted on my P5 A44. Saw the carveout regions
in the boot spew, and CBMEM living just below the last region
(TSEC). Dumped the MC GeneralizedCarveoutX registers and
verified their values (same as BCT, with only BOM/CFG0 changed).

Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: a34b0772cd721193640b322768ce5fcbb4624f23
Original-Change-Id: I2abc872fa1cc4ea669409ffc9f2e66dbbc4efcd0
Original-Signed-off-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/290452
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-(cherry picked from commit f3bbf25397db4d17044e9cfd135ecf73df0ffa60)
Original-Reviewed-on: https://chromium-review.googlesource.com/291081
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>

Change-Id: I924dfdae7b7c9b877cb1c93fd94f0ef98b728ac5
Reviewed-on: http://review.coreboot.org/11381
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-28 06:40:08 +00:00
Yakir Yang 84fb0bfdbb rockchip: rk3288: fix phsync & pvsync bug
Struct edid defien pvsync & phsync as an character,
like '+' or '-', so we need to check sync polarity
by comparing with characters '+' and '-' instead of
treating as boolean.

BRANCH=None
BUG=chrome-os-partner:42946
TEST=Mickey board, light monitor normally

Change-Id: I92d233e19b6df8917fb8ff9a327ccb842c152d65
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: 2d22d4b6e7108474f67200e0fb1e4894cd88db85
Original-Change-Id: I14c72aa8994227092a1059d2b25c1dd2249b9db1
Original-Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/289963
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Queue: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/11380
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-28 06:39:59 +00:00
Aaron Durbin 8d0ab89e5d stdlib: don't hide the malloc et all declarations
It doesn't hurt to expose declarations. Instead of
a compile-time error there'll be a link error if someone
tries to malloc() anything.

Change-Id: Ief6f22c168c660a6084558b5889ea4cc42fefdde
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11406
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
2015-08-27 21:14:10 +00:00
Alexandru Gagniuc d18065b59c packardbell/ms2290/mainboard.c: Do not guard int15 includes
Do not guard the inclusion of "drivers/intel/gma/int15.h"
and "arch/interrupt.h" with configs that control option rom execution.
These headers already have the proper guards. The
install_intel_vga_int15_handler() is unconditionally called, even when
the header that declares it is guarded out.

Change-Id: Ia273437486f5802aa2b53212f2a1b5704c9485fa
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11379
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-27 19:27:09 +00:00
Patrick Georgi 011b0b3af8 cbfstool: update warning on cbfstool extract
We have tons of file types now that can be safely extracted.
It's pretty much only stages and payloads that aren't.

Change-Id: Ibf58a2c721f863d654537850c6f93d68a8a5bbeb
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/11360
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-27 15:07:36 +00:00
Patrick Georgi 83c2d12a3d cbfstool: update help text
cbfstool create doesn't accept alignment configuration anymore.

Change-Id: Idbf7662c605aa78e3d3413a21bfcbc1387f28701
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/11358
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-27 15:07:13 +00:00
Patrick Georgi f5252f378b cbfstool: don't pass header_size as separate argument (part 2)
It's already present inside struct cbfs_file

Change-Id: Ic9682e93c3d208e2ed458940e4a9f9f5a64b6e98
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/11333
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-27 15:07:00 +00:00
Patrick Georgi d5a4afa63d cbfstool: don't pass header_size as separate argument
It's already present inside struct cbfs_file

Change-Id: Ib10663c6601aa02e07b868e440f05da02af9c2d9
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/11332
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-27 15:06:51 +00:00
Patrick Georgi a60e7b6da5 cbfstool: use struct cbfs_file * instead of void *
My concern was that compilers may something stupid under the assumption
of a fixed struct size, but filename is already variable, so things are
okay.

Change-Id: I5348faf68f0a7993294e9de4c0b6c737278b28af
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/11331
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-27 15:01:39 +00:00
Patrick Georgi dc9dbc0059 cbfstool: passing a header is now mandatory for converters
Change-Id: Iea5377af735b06bcaefb999547a8896b1c70763a
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/11330
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-27 15:01:22 +00:00
Patrick Georgi e590358064 cbfstool: cbfs_add_entry() doesn't need to know filename or type
They're passed as part of the header now.

Change-Id: I7cd6296adac1fa72e0708b89c7009552e272f656
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/11327
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-27 15:01:12 +00:00
Martin Roth 422c636683 google/storm/Kconfig: remove select CONSOLE_CBMEM_DUMP_TO_UART
This seems like more of a debug option, than something that should
be forced to be enabled by the platform.  Since it's causing a Kconfig
warning, I'm just removing it.

The alternative to removing it would be to add dependencies on
CONSOLE_CBMEM && !CONSOLE_SERIAL

Change-Id: Ifc4e4cbeea08a503c38827dd75e0e2e78e8a5eda
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/11343
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-08-27 14:50:01 +00:00
Aaron Durbin 5a96b3743e skylake: only generate ACPI cpu entries once
The acpi_fill_ssdt_generator function pointer is evaluated for
each device. As there are multiple cpus in the system the
acpi_fill_ssdt_generator was being called more than once creating
duplicate ACPI entries because there was more than 1 cpu device.
Fix this by only generating them once by removing the
acpi_fill_ssdt_generator for the cpu devices, but add the
generator to the cpu cluster device.

BUG=chrome-os-partner:44084
BRANCH=None
TEST=Built and booted on glados. Noted ACPI entries only generated once.

Original-Change-Id: I695c30e6150f6d3a79d13744c532f1b658b10402
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/294240
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Commit-Queue: Leroy P Leahy <leroy.p.leahy@intel.com>

Change-Id: I7c85f44ba65398bda668e13db8be531535a983c5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11285
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-08-27 14:20:25 +00:00
pchandri 415022a86c skylake: FAB3 Adding Support for various SPD.
This pach enables memory configuration based on PCH_MEM_CFG
and EC_BRD_ID.

BRANCH=None
BUG=chrome-os-partner:44087
CQ-DEPEND=CL:293832
TEST=Build and Boot FAB3 (Kunimitsu)

Original-Change-Id: I7999e609c4b0b3c89a9689ee6bb6b98c88703809
Original-Signed-off-by: pchandri <preetham.chandrian@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/293787
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: I52a1af1683b74e5cad71b9e4861942a23869f255
Signed-off-by: pchandri <preetham.chandrian@intel.com>
Reviewed-on: http://review.coreboot.org/11284
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-08-27 14:19:38 +00:00
Aaron Durbin 028bcaae32 skylake: make PAD_CFG_GPI default to GPIO ownership
The prior implementation of PAD_CFG_GPI kept the pad
ownership as ACPI. The gpio driver in the kernel then
wouldn't allow one to export those GPIOs through sysfs
in /sys/class/gpio. Fix this by setting the ownership
to GPIO.

BUG=chrome-os-partner:44147
BRANCH=None
TEST=Built and boot glados. PCH_WP gpio is properly exported
     by crossystem.

Original-Change-Id: I9fc7ab141a3fd74e0ff8b3ff5009b007b8a0d69b
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/294081
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>

Change-Id: Ifbb61c5d64bb6a04f140685c70f4681e2babecef
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11283
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-08-27 14:19:22 +00:00
Duncan Laurie 56260850e8 glados: Abstract board GPIO configuration in gpio.h
Move all the various places that look at board specific GPIOs into
the mainboard gpio.h so it can be easily ported to new boards.

BUG=chrome-os-partner:40635
BRANCH=none
TEST=build and boot on glados p2

Original-Change-Id: I3f1754012158dd5c7d5bbd6e07e40850f21af56d
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/293942
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: I93c4dc1795c1107a3d96e686f03df3199f30de8a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/11282
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-08-27 14:19:09 +00:00
Duncan Laurie c328191728 glados: Implement Chrome OS specific handlers
Implement the required Chrome OS specific handlers to read the
recovery mode, clear the recovery mode, read the lid switch state,
and read the write protect state using the appropriate methods.

Also update the Chrome OS ACPI device to use the GPIO definitions
that are exposed now by the SOC.

BUG=chrome-os-partner:43515
BRANCH=none
TEST=build and boot on glados and successfully enter recovery mode

Original-Change-Id: Ifd51c11dc71b7d091615c29a618454a6a2cc33d7
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/293515
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: Ia6ef83a80b9729654bc87bb81bd8d7c1b01d7f42
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/11281
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-27 14:18:54 +00:00
Duncan Laurie 699c788837 chromeec: Add helper function to read EC switch state
Add a helper function to read the EC switch state on LPC based
ECs instead of having each board need to understand and use the
specific EC LPC IO method that is required.

BUG=chrome-os-partner:43515
BRANCH=none
TEST=build and boot on glados

Original-Change-Id: Id046c7ddf3a1689d4bf2241be5da31184c32c0e1
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/293514
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: Id11009e0711b13823e4f76dc9db9c9c20abf4809
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/11280
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-27 14:18:38 +00:00
Duncan Laurie 7f3f285bf1 glados: Fix SPD part number for Hynix H9CCNNN8JTBLAR
The part number was the same as the H9CCNNNBLTLAR which means it
is not possible to distinguish the two based on part number alone.
This breaks mosys and thus the factory tests.

BUG=chrome-os-partner:43514
BRANCH=none
TEST=boot on glados P2 SKU3 and verify memory reported by mosys

Original-Change-Id: I606ef3989bd7273d134a258bc933088ccc865542
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/293513
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: I7cea7cc4c61a20fda47673c8e25c431d391aa3bc
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/11279
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-27 14:18:29 +00:00
Duncan Laurie a40b7f3e1d glados: Add touchscreen device in ACPI
Add the ELAN touchscreen device in ACPI to bind it to the I2C
device at bus I2C0, address 0x10, interrupt 31 (GPP_E7).

BUG=chrome-os-partner:43514
BRANCH=none
TEST=boot on glados P2 and see touchscreen initialized by kernel

Original-Change-Id: I23b071b2767547baed239c94216cda6162d045dd
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/293512
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: I8a9492e6fa1f650cef0871329ae8944caffdaf5a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/11278
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-27 14:18:17 +00:00
Duncan Laurie 35a32064f1 glados: Clean up mainboard ACPI devices
Clean up the device code for the glados mainboard, using
the defined values for interrupts by the SOC and moving the
various codec i2c addresses to the top of the file.

BUG=chrome-os-partner:40635
BRANCH=none
TEST=build and boot on glados

Original-Change-Id: Iead1aeb54363b15a6176d4f4a9511674195c0505
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/293511
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: I083c9ef6140e20a433cb2017e4c3cbc7a41e8fed
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/11277
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-27 14:18:06 +00:00
Naveen Krishna Chatradhi 5eed3a5518 kunimitsu: Enable SMBus device in devicetree
this patch enables SMBus in device tree for kunimitsu board.

BRANCH=none
BUG=none
TEST=built for kunimitsu; booted on kunimitsu fab3 and verified with
lspci

Original-Change-Id: I3b2b8c202b71c2a0c602169841978ed0c4d8bf8d
Original-Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292971
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: Id20e6cafda8664bd0ae3a5acecdd66c58c220694
Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch@intel.com>
Reviewed-on: http://review.coreboot.org/11276
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-27 14:17:56 +00:00
pchandri 3657eef829 Kunimitsu : FAB3 Adding BoardId support
BRANCH=None
BUG=chrome-os-partner:44087
TEST=Build and Boot kunimitsu.

Original-Change-Id: I30ba8bad69a4fdf8ec29f9eb43a27d2e1c6b93dd
Original-Signed-off-by: pchandri <preetham.chandrian@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/293832
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: I8f85547865387091c9a6400611e3314f457076d5
Signed-off-by: pchandri <preetham.chandrian@intel.com>
Reviewed-on: http://review.coreboot.org/11275
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-27 14:17:37 +00:00
Naveen Krishna Chatradhi 133dcd386f Kunimitsu: enable deep S5
This patche enables the deep S5 and disables Deep S3.
Kunimitsu does not resume from deep S3. This change will
unblock the S3 resume path on kunimitsu board.

BRANCH=None
BUG=chrome-os-partner:42331
TEST=Built and booted on kunimitsu; check s3 works.

Original-Change-Id: Ia828a39bceef615fd194bb3614ba2de87c3af805
Original-Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/291250
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: I07b95a324a27ab658e80674686b47b86412ea097
Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch@intel.com>
Reviewed-on: http://review.coreboot.org/11274
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-27 14:16:30 +00:00
Thaminda Edirisooriya 31f0521a99 riscv-trap-handling: Add preliminary trap handling for riscv
RISCV requires a trap handler at the machine stage to deal with
misaligned loads/stores, as well as to deal with calls that a linux
payload will make in its setup. Put required assembly for jumping
into and out of a trap here to be set up by the bootblock in a later
commit.

Change-Id: Ibf6b18e477aaa1c415a31dbeffa50a2470a7ab2e
Signed-off-by: Thaminda Edirisooriya <thaminda@google.com>
Reviewed-on: http://review.coreboot.org/11367
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2015-08-26 23:50:45 +00:00
Roger Pau Monne 5cd34e2f15 inteltool: fix build for FreeBSD
Replace usage of u<bitness> types with proper uint<bitness>_t types.

Change-Id: I8359d70304a138b29bfc1358af77af26b2bc8682
Signed-off-by: Roger Pau Monne <roger.pau@citrix.com>
Reviewed-on: http://review.coreboot.org/11364
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-26 15:47:00 +00:00
Martin Roth e2473c5950 Chromeos: Remove Kconfig workaround for VIRTUAL_DEV_SWITCH warnings
With VIRTUAL_DEV_SWITCH moved under 'config CHROMEOS' in all of the
mainboards, this is no longer needed.

Change-Id: I5fbea17969f6b0c3b8a5dcd519ab9d36eb2ad6f1
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/11337
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-26 15:46:09 +00:00
Martin Roth 8c12d6e823 ChromeOS mainboards: Move more Kconfig symbols under CHROMEOS
Move the CHROMEOS dependent symbols VIRTUAL_DEV_SWITCH and
VBOOT_DYNAMIC_WORK_BUFFER under the CHROMEOS config options for the
mainboards that use them.

Change-Id: Iad126cf045cb3a312319037aff3c4b1f15f6529d
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/11336
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
2015-08-26 15:45:36 +00:00
Martin Roth 870d3de270 hp/dl165_g6_fam10/Kconfig: remove unused QRANK_DIMM_SUPPORT
AMD family 10 boards don't use QRANK_DIMM_SUPPORT.

Change-Id: Id7e1fba86e2ea1d4d5f5c2e123bd36ad802fd15e
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/11344
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-08-26 15:09:15 +00:00
Martin Roth c0c115b657 Google Kconfig: Add MAINBOARD_HAS_NATIVE_VGA_INIT in good places
Add 'select MAINBOARD_HAS_NATIVE_VGA_INIT' which is just used as a gate
symbol to display MAINBOARD_DO_NATIVE_VGA_INIT to the mainboards that
are already selecting MAINBOARD_DO_NATIVE_VGA_INIT.

Since MAINBOARD_HAS_NATIVE_VGA_INIT is not used in any code, this should
not have any other effects.

This fixes the warning:
warning: (BOARD_SPECIFIC_OPTIONS) selects MAINBOARD_DO_NATIVE_VGA_INIT
which has unmet direct dependencies (VENDOR_ASUS && BOARD_ASUS_KFSN4_DRE
|| MAINBOARD_HAS_NATIVE_VGA_INIT)

Change-Id: I8ceee69ebae90dc32f55df58c2e80fe25397f049
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/11301
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-26 15:08:49 +00:00
Patrick Georgi 3ba501b86d cbfstool: move cbfs_file header creation further up the call chain
The header is now created before the "converters" are run.
Adding new capabilities (and fields to the header) will happen there,
so we're close.

Change-Id: I0556df724bd93816b435efff7d931293dbed918f
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/11326
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-26 12:22:14 +00:00
Patrick Georgi 056f6a1f80 cbfstool: pass cbfs_file header into "compress" functions
These functions can do all kinds of things, such as converting an ELF
image into SELF, or (in the future) compress or checksum entire files.
This may require changing or adding fields to the header, so they
need to have access to it.

The header_size parameter that was provided (but never used) is
equivalent to cbfs_file's offset field.

Change-Id: I7c10ab15f3dff4412461103e9763a1d78b7be7bb
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/11325
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-26 12:21:49 +00:00
Patrick Georgi 19c80b2391 cbfstool: drop size argument to cbfs_add_entry_at
It's sole use was comparing it to the header's "len" field.

Change-Id: Ic3657a709dee0d2b9288373757345a1a56124f37
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/11324
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-26 12:21:30 +00:00
Patrick Georgi ae7efb9257 cbfstool: cut down on the debug output
Change-Id: I9a0aad42e4eb67a07c939d7cfa0d2d80838412bb
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/11323
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-26 12:21:20 +00:00
Patrick Georgi 7a33b53dc0 cbfstool: Don't patch cbfs_file->len, it's already set correctly
->len used to be set to the file data length plus the size of the
padding used for the cbfs_file header. This isn't the case anymore,
so no patching of this field is necessary anymore.

->offset still needs to be patched in that case because its final
value can only be determined when the file's actual location is known.

Change-Id: I1037885f81b4ed3b68898dd7d0e515cf7a9c90a8
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/11322
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-26 12:20:55 +00:00
Patrick Georgi bc39690900 cbfstool: drop unused arguments in internal function
Change-Id: Ie4edc5f9c96ffba7dcf8b974c56851658b9538e4
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/11321
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-26 12:20:39 +00:00
Patrick Georgi 62c014bcf3 cbfstool: start moving cbfs_file header creation up the call chain
Up to now cbfstool creates the cbfs_file header at the latest possible
time, which is unsuitable when the idea is to add further fields to it
that need to be configured earlier.

Thus, have it ripple up the call chain.

Change-Id: I7c160681c31818bc550ed2098008146043d0ee01
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/11320
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-26 12:20:24 +00:00
Patrick Georgi 4eb8abeb85 cbfstool: more descriptive variable name
"target", for what? It's the offset where the file header of the currently
added file will be located, name it as such.

Change-Id: I382f08f81991faf660e217566849773d9a7ec227
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/11319
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-26 12:20:08 +00:00
Jonathan A. Kollasch 64fc433a56 crossgcc: rename source file names from gcc-5.2.0/* to binutils-2.25/* in binutils riscv patches
Followup-To: I6f37748b4cf0852d292f8f5156fc27ab8fd481b6

Change-Id: Ib6599b2380b5f2efd92ae78b72b45f3d65681379
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/11329
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2015-08-26 01:39:25 +00:00
zbao 06e85acb40 buildgcc: Move a bunch of code into a function
Refactor the code to be better understandable.

Change-Id: Ia815a27f7cc83c226a32e87485d712a5fbf4168e
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/11318
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-26 01:06:17 +00:00
Martin Roth df205067c9 Intel: Remove CACHE_MRC_BIN - 'selected' everywhere in Kconfig
The Kconfig symbol CACHE_MRC_BIN was getting forced enabled everywhere
it existed.

Remove the Kconfig symbol and get rid of the #if statements
surrounding the code.

This fixes the Kconfig warning for Haswell & Broadwell chips:
warning: (NORTHBRIDGE_INTEL_HASWELL &&
NORTHBRIDGE_INTEL_SANDYBRIDGE &&
NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE &&
NORTHBRIDGE_INTEL_IVYBRIDGE &&
NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE &&
CPU_SPECIFIC_OPTIONS) selects CACHE_MRC_BIN
which has unmet direct dependencies
(CPU_INTEL_SOCKET_RPGA988B || CPU_INTEL_SOCKET_RPGA989)

Change-Id: Ie0f0726e3d6f217e2cb3be73034405081ce0735a
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/11270
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-25 17:36:45 +00:00
Martin Roth 1fff0d26f8 xcompile: Force localization of objdump to C
In testing other localization changes, I found that I couldn't build
anymore because xcompile wasn't picking up my toolchain.  I traced it
to the regex comparison of '.*format \(.[a-z0-9-]*\)' to the string
'formato del fichero elf32-i386'.  Forcing the localization of
objdump to C before doing the comparison fixes the issue.

Change-Id: I6bed5a9824807dd5bc5a38b711ab47e2af4b0c29
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/11304
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Zheng Bao <zheng.bao@amd.com>
2015-08-25 15:40:44 +00:00