4 Commits

Author	SHA1	Message	Date
Arthur Heymans	6d0c65ebc6	nb/intel/*/northbridge.c: Remove #include <device/hypertransport.h> ... Nothing from that header is used or even declared since CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not selected on Intel hardware. Change-Id: I9101eb6ffa6664a2ab45bc0b247279c916266537 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/18044 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Idwer Vollering <vidwer@gmail.com>	2017-01-06 18:15:03 +01:00
Kyösti Mälkki	27198ac2e3	MMCONF_SUPPORT: Drop redundant logging ... Resource is actually stored even before read_resources, but that's where we currently log this resource. For Intel, use PCI config register offset as the resource index, while AMD side uses MSR address. Change-Id: I6eeef1883c5d1ee5bbcebd1731c0e356af3fd781 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17696 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>	2016-12-07 13:04:58 +01:00
Kyösti Mälkki	e25b5ef39f	MMCONF_SUPPORT: Consolidate resource registration ... Change-Id: Id727270bff9e0288747d178c00f3d747fe223b0f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17695 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>	2016-12-07 13:00:56 +01:00
Stefan Reinauer	4bab6e79b0	intel/sch: Merge northbridge and southbridge in src/soc ... Change-Id: I6ea9b9d2353c0d767c837e6d629b45f23b306f6e Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14599 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>	2016-05-17 21:38:17 +02:00

Renamed from src/northbridge/intel/sch/northbridge.c (Browse further)