Commit Graph

19711 Commits

Author SHA1 Message Date
Matt DeVillier 91480cc64c Makefile.inc: export VARIANT_DIR as top-level variable
export VARIANT_DIR at the top level, rather than doing so multiple
times at the SoC / board level

Change-Id: If825701450c78289cb8cca731d589e12aafced11
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/17451
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-18 20:28:37 +01:00
Nicola Corna f1395d825b ec/lenovo/h8: Add USB Always On
USB AO is the internal name for the dedicated charging port on
ThinkPads when in S3 or lower.

AOEN (bit 0) is internal name for enabling this feature while AOCF
(bits 2 and 3) is the configuration field. According to Peter Stuge,
AOCF can be configured in this way:

    00 => AC S3 S4 S4 USB on, battery S3 USB on, battery S4 S5 off
    11 => AC S3 S4 S4 USB on, battery S3 S4 S5 USB off
    10, 01 => equivalent to 00

This commit also adds a new configuration field in the CMOS of the
X220 and the X201 to activate this feature. It probably can be also
added to all the ThinkPads that support this functionality.

With this functionality USB devices are able to negotiate full power
from the dedicated port (usually the yellow one) even in S3.

Tested on a X201 and X220 with an Android smartphone: with this
feature enabled it shows "Charging" when connected during S3, without
it it shows "Charging slowly" (or it doesn't charge at all on the
X201).

For some reasons the "AC only" mode doesn't work, so it has been
disabled.

Change-Id: Ie1269a4357e2fbd608ad8b7b8262275914730f6e
Signed-off-by: Nicola Corna <nicola@corna.info>
Reviewed-on: https://review.coreboot.org/17252
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-11-18 18:14:42 +01:00
Furquan Shaikh cd2afc0df0 google/chromeec: Add common infrastructure for boot-mode switches
Instead of defining the same functions for reading/clearing boot-mode
switches from EC in every mainboard, add a common infrastructure to
enable common functions for handling boot-mode switches if
GOOGLE_CHROMEEC is being used.

Only boards that were not moved to this new infrastructure are those
that do not use GOOGLE_CHROMEEC or which rely on some mainboard specific
mechanism for reading boot-mode switches.

BUG=None
BRANCH=None
TEST=abuild compiles all boards successfully with and without ChromeOS
option.

Change-Id: I267aadea9e616464563df04b51a668b877f0d578
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17449
Tested-by: build bot (Jenkins)
Reviewed-by: Julius Werner <jwerner@chromium.org>
2016-11-18 04:01:59 +01:00
Marshall Dawson f8a274acf5 rtc: Force negative edge on SET after battery replacement
After the RTC coin cell has been replaced, the Update Cycle Inhibit
bit must see at least one low transition to ensure the RTC counts.
The reset value for this bit is undefined. Examples have been observed
where batteries are installed on a manufacturing line, the bit's state
comes up low, but the RTC does not count.

Change-Id: I05f61efdf941297fa9ec90136124b0c8fe0639c6
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/17370
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-17 23:08:59 +01:00
Marshall Dawson 5a043fe08d rtc: Check update-in-progress bit
While the real-time clock updates its count, values may not be correctly
read or written.  On reads, ensure the UIP bit is clear which guarantees
a minimum of 244 microseconds exists before the update begins.  Writes
already avoid the problem by disabling the RTC count via the SET bit.

Change-Id: I39e34493113015d32582f1c280fafa9e97f43a40
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/17369
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-17 23:08:43 +01:00
Naresh G Solanki 05abe4351b arch/x86/acpigen: Implement acpigen functions to return integer & string
Add ACPI method to return integer & string.

Change-Id: I2a668ccadecb71b71531e2eb53a52015fca96738
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/17450
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-17 21:09:27 +01:00
Wisley Chen 676b487897 google/snappy: Update DPTF settings
1. Update DPTF CPU/TSR1/TSR2 passive/critial trigger points.
   CPU passive point:100, critical point:105
   TSR1 passive point:48, critial point:65
   TSR2 passive point:85, critial point:100

2. Update PL1/PL2 Min Power Limit/Max Power Limit
   Set PL1 min to 3W, and max to 6W
   Set PL2 min and max to 8W

3. Change thermal relationship table (TRT) setting.
   The TRT of TCHG is TSR1, but real sensor is TSR2.

BRANCH=master
BUG=none
TEST= Compiled, verified by thermal team.

Change-Id: Ib197c36eca88e3d05f632025cf3c238e1a2eae23
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/17426
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-17 18:48:49 +01:00
Jagadish Krishnamoorthy 9f2a411042 mainboard/google/reef: disable unused devices
The following devices i2c6, i2c7, spi1, spi2, uart3
are not used.

BUG=chrome-os-partner:59880
TEST=Boot to OS and lspci command should
not list the above disabled devices.

Change-Id: I819cdb34709703e6431b49446417ed9d6b3543cd
Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com>
Reviewed-on: https://review.coreboot.org/17441
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-17 18:48:14 +01:00
Naresh G Solanki df921ff7ae mb/intel/kblrvp: Remove unused configs in Kconfig
Remove unused drivers & nhlt in Kconfig.

Change-Id: Ic1e8a98a77a0061e749019665f955b921f85975e
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/17427
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-17 18:47:26 +01:00
Aaron Durbin a20e983236 mainboard/google/reef: set i2c bus timings by rise/fall times
Provide the rise and fall times for the i2c buses and let the
library perform the necessary calculations for the i2c
controller registers instead of manually tuning the values.

BUG=chrome-os-partner:58889,chrome-os-partner:59565

Change-Id: I0c84658471d90309cdbb850e3128ae01780633af
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17397
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
2016-11-17 18:46:58 +01:00
Derek Basehore 96831e69a0 google/gru: Move to one CA training pattern
This changes memory to only do CA training with one pattern,
0xfffff/0x00000 and to also make sure CA training waits for all of the
captures during training.

BRANCH=none
BUG=chrome-os-partner:56940
TEST=boot kevin and run
stressapptest -M 1500 -s 1000

Change-Id: I0982674b4f4415f4d7865923ced93fa09bdd877e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 75cdd911cea9c4e5744fd04505b260fa5755513c
Original-Change-Id: I3b86e6d4662c6fbbf9ddef274fce191a367904e5
Original-Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/410320
Original-Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-on: https://review.coreboot.org/17383
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-17 18:45:35 +01:00
Derek Basehore 00ad7ff1ca google/gru: Add new CA training pattern
This adds a new CA training pattern for all of the supported
frequencies. This pattern increases the hold time on CA.

BRANCH=none
BUG=chrome-os-partner:57845
TEST=boot kevin and run:
while true; do sleep 0.1; memtester 500K 1 > /dev/null; done
for several hours

Change-Id: Ie5958cf67c16247ef90ee261da9faef4ffa5b339
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8babeafe75bffcb2dab17eb007b4f5bb0eb42606
Original-Change-Id: I7f7652f88e43dc9b2f6069e60514931bf7582ed1
Original-Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/403547
Original-Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-on: https://review.coreboot.org/17382
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-17 18:00:43 +01:00
PH Hsu b4946a9e65 google/oak: Add more DRAM modules support
Add support for following 3 modules.
- Micro MT52L256M32D1PF / MT52L512M32D2PF
- Hynix H9CCNNNBJTALAR

Hana EVT was planed to add 4 DRAM modules but RAM_CODE=5 is not used
in the end.
This patch also unifies the naming of the RAM configurations.

BUG=chrome-os-partner:58983
TEST=verified on Hana EVT.

Change-Id: I7dd44525de8e9dde01f210f4730fa8ccd4baef21
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5dccd68149bcfd6fd0a83e310d43063bab645691
Original-Change-Id: I7c245c8c24be159e152f4f3cca25bf970b58425c
Original-Signed-off-by: Milton Chiang <milton.chiang@mediatek.com>
Original-Signed-off-by: PH Hsu <ph.hsu@mediatek.com>
Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/402888
Original-Reviewed-by: Pin-Huan Hsu <ph.hsu@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Paris Yeh <pyeh@chromium.org>
Reviewed-on: https://review.coreboot.org/17381
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-17 18:00:27 +01:00
Julius Werner 50e76709ed arm64: arm_tf: Do not build raw bl31.bin binary
coreboot's build system picks up the BL31 image as an ELF from the ARM
Trusted Firmware submodule and inserts it into CBFS. However, the
generic 'bl31' build target we run in the ARM Trusted Firmware build
system also generates a raw bl31.bin binary file.

We don't need that binary, and with the recently added support for
multiple non-contiguous program segments in BL31 it can grow close to
4GB in size (by having one section mapped near the start and one near
the end of the address space). To avoid clogging up people's hard drives
with 4GB of zeroes, let's only build the target we actually need.

BRANCH=gru
BUG=chrome-os-partner:56314,chromium:661124
TEST=FEATURES=noclean emerge-kevin coreboot, confirm that there's no
giant build/3rdparty/arm-trusted-firmware/bl31.bin file left in the
build artifacts, and that we still generate .d prerequisite files.

Change-Id: I8e7bd50632f7831cc7b8bec69025822aec5bad27
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 31699820f4c36fd441a3e7271871af4e1474129f
Original-Change-Id: Iaa073ec11dabed7265620d370fcd01ea8c0c2056
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/407110
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17380
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-17 18:00:09 +01:00
Derek Basehore 8e1a99546b rockchip/rk3399: Change 933 DPLL to low jitter rate
This changes the 933 DPLL rate to 928 which has low jitter.

BRANCH=none
BUG=chrome-os-partner:57845
TEST=boot kevin and run
while true; do sleep 0.1; memtester 500K 1 > /dev/null; done
for several hours

Change-Id: I4d2a8871aaabe3b0a1a165c788af265c5f9e892c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 54ebf8763bb8193c4b36a5e86f0c625b176d31a6
Original-Change-Id: Iaa12bf67527b6d0e809657c513b8d1c66af25174
Original-Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/404550
Original-Reviewed-by: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/17379
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-17 17:59:22 +01:00
Julius Werner 8e42bd1cbc rockchip/rk3399: Change PLL configuration to match Linux kernel
The Kevin project has been too smooth and boring for our tastes in the
last last few weeks, so we've decided to stir the pot a little bit and
reshuffle all our PLL settings at the last minute. The new settings
match exactly what the Linux kernel expects on boot, so it doesn't need
to reinitialize anything and risk a glitch.

Naturally, changing PLL rates will affect child clocks, so this patch
changes vop_aclk (192MHz -> 200MHz, 400MHz in the kernel), pmu_pclk
(99MHz -> 96.57MHz) and i2c0_src (198MHz -> 338MHz, leading to an
effective I2C0 change 399193Hz -> 398584Hz).

BRANCH=gru
BUG=chrome-os-partner:59139
TEST=Booted Kevin, sanity checking display and beep. Instrumented
rockchip_rk3399_pll_set_params() in the kernel and confirmed that GPLL,
PPLL and CPLL do not get reinitialized anymore (with additional kernel
patch to ignore frac divider when it's not used). Also confirmed that
/sys/kernel/debug/clk_summary now shows pclk_pmu_src 96571429 because
the kernel doesn't even bother to reinitialize the divisor.

Change-Id: Ib44d872a7b7f177fb2e60ccc6992f888835365eb
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9b82056037be5a5aebf146784ffb246780013c96
Original-Change-Id: Ie112104035b01166217a8c5b5586972b4d7ca6ec
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/405785
Original-Commit-Ready: Xing Zheng <zhengxing@rock-chips.com>
Original-Tested-by: Xing Zheng <zhengxing@rock-chips.com>
Original-Reviewed-by: Xing Zheng <zhengxing@rock-chips.com>
Original-Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-on: https://review.coreboot.org/17378
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-17 17:59:09 +01:00
Martin Roth c295d5e249 crossgcc/buildgcc: Add package version to saved .success file
Previously, the .success file for each target didn't save the version,
of the package that was built.  This created problems when someone
wanted to update to a new version and could not rebuild.

Change-Id: I9975b198ac4a7de8ff9323502e1cbd0379a1dbb8
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/17417
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-17 17:57:47 +01:00
Martin Roth b9e8ad8f68 soc/broadcom/cygnus: Update DDR Kconfig
The DDR speed Kconfig symbols needed to either be added to the Kconfig
tree, or have the code associated with them removed.  I chose to add
the symbols.

- Add symbols for DDR333 - DDR667 to cygnus Kconfig.  These should be
selected by the mainboard.
- Rename symbols from DDRXXX to CYGNUS_DDRXXX to match the existing
CYGNUS_DDR800 symbol.
- Rename the non Kconfig #define CONFIG_DRAM_FREQ to CYGNUS_DRAM_FREQ
because having other #defines look like Kconfig symbols is confusing.
- Change #ifdef CONFIG_DDRXXX to use IS_ENABLED

Change-Id: I3f5957a595072434c21af0002d57ac49b48b1e43
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/17386
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
2016-11-17 17:57:09 +01:00
Nelson, Cole 1cf5b87f48 soc/intel/apollolake: Enable and Lock AES feature register
Configure MPinit feature register during boot and s3 resume.
Enable and Lock Advanced Encryption Standard (AES-NI) feature.

BUG=chrome-os-partner:56922
BRANCH=None

Change-Id: Id16f62ec4e7463a466c43d67f2b03e07e324fa93
Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Reviewed-on: https://review.coreboot.org/17396
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-17 15:18:47 +01:00
Nico Huber e34e178ca3 sio/ite/common: Add generic environment-controller driver
The environment-controller entity is shared by many ITE super-i/o
chips. There are some differences between the chips, though. To cover
that, the super-i/o chip should select Kconfig options of this driver
accordingly.

The current implementation isn't exhaustive: It covers only those
parts that are connected on boards I could test, plus those that are
currently used by the IT8772F. The latter could be ported to use this
driver if somebody minds to test it.

Change-Id: I7a40f677f667d103ce1d09a3e468915729067803
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/17284
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-17 11:27:38 +01:00
Naresh G Solanki c70cc4d70d arch/x86/acpigen: acpigen buffer size fix
In function definition of acpigen_write_byte_buffer, buffer size written
using acpigen_emit_byte gives wrong results in generated AML code for
buffer size greater than one.

Write buffer size using acpigen_write_integer as per ACPI spec 5.0
section 20.2.5.4 BufferOp.

Change-Id: I0dcb25b24a1b4b592ad820c95f7c2df67a016594
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/17444
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-11-17 09:52:54 +01:00
Barnali Sarkar d899318b78 drivers/i2c/alps: Add support for ALPS Touchpad driver
Add support for I2C ALPS Touchpad Device Driver.

BUG=none
BRANCH=none
TEST=Build and booted successfully on KBL RVP and Touchpad is working

Change-Id: I78b77bd7c4694ccf61260724f593bd59545c70e6
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/17390
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-11-16 19:42:29 +01:00
Elyes HAOUAS dab15e2491 include/device/pci_ids.h: Correct Entertainment sub-class
According to PCI LOCAL BUS SPECIFICATION, REV. 3.0 page 305,
the sub-class for Entertainment en/decryption is 0x1010

Change-Id: Ia069e2ec328a8180fc1e2e70146c3710e703ee59
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/17436
Tested-by: build bot (Jenkins)
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-11-16 19:11:57 +01:00
David Imhoff 4ae054068a intel/fsp_baytrail: Fix assignment of PcdeMMCBootMode
Before the PcdeMMCBootMode in the Updatable Product Date was always
assigned and didn't take into account the + 1 increment for the default
define.

Now if the configuration indicates that the device tree should be
followed PcdeMMCBootMode is initially disabled. Else if configuration
isn't the default, assign the value with the + 1 increment substracted.

TEST=Intel/MinnowMax

Change-Id: I6755eb585d1afe3a15f83347fba834766eb44ad2
Signed-off-by: David Imhoff <dimhoff_devel@xs4all.nl>
Reviewed-on: https://review.coreboot.org/10165
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-16 18:23:11 +01:00
David Imhoff 24f5164a26 intel/fsp_baytrail: Always log PcdEnableLpe and PcdeMMCBootMode
Log the values of PcdEnableLpe and PcdeMMCBootMode even if they are
outside of the expected range.

TEST=Intel/MinnowMax

Change-Id: Ie0aea4287234b23d4e9852f3991dcc78ce8103d9
Signed-off-by: David Imhoff <dimhoff_devel@xs4all.nl>
Reviewed-on: https://review.coreboot.org/10164
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-16 18:22:20 +01:00
Sathyanarayana Nujella b7d44dfcf5 mainboard/google/reef: Add proper DMIC endpoints based on DMIC config pin
Reef board uses GPIO_17 as DMIC config pin.
This pin distinguishes board with Quad DMIC's or Mono DMIC.
This patch adds necessary DMIC endpoints to support either of
those configurations.

CQ-DEPEND=CL:*304339,CL:409774

BUG=chrome-os-partner:56918
BRANCH=none
TEST=Verify Mono and Quad Channel DMIC record

Change-Id: I5b2825b5f39f8962985a129f8ec65265fb18f0b2
Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-on: https://review.coreboot.org/17158
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-11-16 18:11:44 +01:00
Arthur Heymans 37d15c6cab mb/ga-945gcm-s2l: Clean up Superio
GPIO register at offset 0xfc (VID Input Register) is read-only but
writing 1 to bit 0 will update initial VID input.

Change-Id: Ie372e98f8e497eede382975262a63d58c16227b9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17412
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-16 18:10:14 +01:00
Duncan Laurie 28726d1cec google/eve: Fill out memory ID table
Add the DIMM SPD data for memory types that are not used yet
but are on the matrix and may be used in future builds.

Also fix a typo in the part number string for one type.

BUG=chrome-os-partner:58666
TEST=build and boot on eve p0

Change-Id: I20401d7afb69f1c3ae1a3b0d6e3ec9097f54ef96
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/17437
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-16 17:38:57 +01:00
Vadim Bendebury 3883701d5a vboot: make TPM factory init sequence more robust.
Currently the code considers the absence of the NVRAM firmware
rollback space a a trigger for invoking the TPM factory initialization
sequence.

Note that the kernel rollback and MRC cache hash spaces are created
after the firmware rollback space. This opens an ever so narrow window
of opportunity for bricking the device, in case a startup is
interrupted after firmware space has been created, but before kernel
and MRC hash spaces are created.

The suggested solution is to create the firmware space last, and to
allow for kernel and MRC cache spaces to exist during TPM factory
initialization.

BRANCH=none
BUG=chrome-os-partner:59654
TEST=odified the code not to create the firmware space, wiped out the
     TPM NVRAM and booted the device. Observed it create kernel and
     MRC cache spaces on the first run, and then reporting return code
     0x14c for already existing spaces on the following restarts.

     Verified that the device boots fine in normal and recovery modes
     and TPM NVRAM spaces are writeable in recovery mode.

Change-Id: Id0e772448d6af1340e800ec3b78ec67913aa6289
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/17398
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-11-16 02:16:11 +01:00
Vadim Bendebury af8ae93172 vboot: TPM2 - report attempts to re-create NVRAM spaces
Currently the tlcl_define_space() function returns the same error
value for any non-zero TPM response code. The thing is that the caller
might want to allow attempts to re-create existing NVRAM spaces. This
patch adds a new API return value to indicate this condition and uses
it as appropriate.

BRANCH=none
BUG=chrome-os-partner:59654
TEST=for test purposes modified the code not to create the firmware
     space, wiped out the TPM NVRAM and booted the device. Observed it
     create kernel and MRC index spaces on the first boot and then
     reporting return code 0x14c for already existing spaces on the
     following restarts.

Change-Id: Ic183eb45e73edfbccf11cc19fd2f64f64274bfb2
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/17422
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-16 02:15:58 +01:00
Furquan Shaikh 1fc6bb9382 arch/x86/acpigen: Fix acpigen for If (Lequal (...))
acpigen_write_if_lequal is used to generate ACPI code to check if two
operands are equal, where operand1 is an ACPI op and operand2 is an
integer. Update name of function to reflect this and fix code to write
integer instead of emitting byte for operand2.

TEST=Verified by disassembling SSDT on reef that ACPI code generated for
If with operand2 greater than 1 is correct.

If ((Local1 == 0x02))
{
	Return (0x01)
}
Else
{
	Return (Buffer (One)
	{
		0x00                          /* . */
	})
}

Change-Id: If643c078b06d4e2e5a084b51c458dd612d565acc
Reported-by: Naresh G Solanki <naresh.solanki@intel.com>
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17421
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-16 01:08:06 +01:00
Nico Huber 6444b52ce0 Revert "ec/lenovo/h8: don't load configuration when booting from s3"
This reverts commit 83df672d2c.

It's based on the assumption that the H8 keeps its configuration
during a suspend/resume cycle. User reports indicate that this might
not be true.

Caching the settings in a cbtable entry might be a better approach.

Change-Id: Ic4ba862ee7068ffe214c2aeaadecb4390a0e0529
Reviewed-on: https://review.coreboot.org/17411
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2016-11-16 00:47:59 +01:00
Furquan Shaikh 0530b29921 intel/apollolake: Ensure SPI operations do not cross 256-byte boundary
BIOS needs to ensure that SPI write does not cross 256-byte
boundary. Else, if the write is across 256-byte boundary, then it
corrupts the block by wrapping write to start of current block. Thus,
ensure nuclear_spi_{read,write} operate within a single 256-byte block
only at a time.

BUG=chrome-os-partner:59813
BRANCH=None
TEST=Verified that elog writes do not corrupt the event log when write
is across 256-byte blocks.

Change-Id: I854ca2979d65b9f1232f93182cb84d4dee4f4139
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17419
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-15 22:21:07 +01:00
Antonello Dettori a2f1d18921 northbridge/via/vx800: transition away from device_t
Replace the use of the old device_t definition inside
northbridge/via/vx800.

Change-Id: I14a2b4d847f8aeb327d90f385dea998779fae24f
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/17316
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-15 18:21:30 +01:00
Antonello Dettori 8e930c1036 northbridge/via/cx700: transition away from device_t
Replace the use of the old device_t definition inside
northbridge/via/cx700.

Change-Id: I6e25f898ab55ee959f1b3b8aba9616c3ba18986d
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/17315
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-15 18:20:20 +01:00
Antonello Dettori 28139522a7 northbridge/intel/i855: transition away from device_t
Replace the use of the old device_t definition inside
northbridge/intel/i855.

Change-Id: Iae66d1ef838095a560868d9c9ff81f4208f814f1
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/17314
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-15 18:19:44 +01:00
Antonello Dettori 17f3c0f6a2 northbridge/amd/agesa/family10: transition away from device_t
Replace the use of the old device_t definition inside
northbridge/amd/agesa/family10.

Change-Id: I5723e217fc739ab576cbe3a1ee6d92023190267c
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/17313
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-15 18:19:30 +01:00
Antonello Dettori 50f1b1aab5 mainboard/via/vt8454c: transition away from device_t
Replace the use of the old device_t definition inside
mainboard/via/vt8454c.

Change-Id: I94e22e1d814733c4049e78e5b3c23b9bb429f6fa
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/17312
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-15 18:19:12 +01:00
Antonello Dettori d4d265e9fe mainboard/via/epia-m700: transition away from device_t
Replace the use of the old device_t definition inside
mainboard/via/epia-m700.

Change-Id: I7a16a9f396d50279cf2bd13de72bd78e8f53f7d8
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/17311
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-15 18:17:47 +01:00
Antonello Dettori 825b801588 mainboard/via/epia-cn: transition away from device_t
Replace the use of the old device_t definition inside
mainboard/via/epia-cn.

Change-Id: I1b05abcedc427e4876e1fdab85298015308a3d17
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/17310
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-15 18:17:10 +01:00
Antonello Dettori c63ee26eca mainboard/tyan/s8226: transition away from device_t
Replace the use of the old device_t definition inside
mainboard/tyan/s8226.

Change-Id: I41729fc03518a7804ae224c773967453a7ab60a7
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/17309
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-15 18:16:38 +01:00
Iru Cai 9f1f1e0cb8 google/link/i915.c: Fix build error when native gfx init enabled
- Move members of struct edid to struct edid_mode
- Change `u32 pmmio` to `u8 *pmmio` in i915_lightup_sandy

Change-Id: Id64daf5eae1d4d8265105067b2e6ae55786a5638
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/17332
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-11-15 18:10:30 +01:00
Arthur Heymans eeaf9e4687 nb/gm45: Refactor IGD vram decoding
This is more consistent with other Intel GMCH code.

Change-Id: I7bfaa79b9031e2dcc5879a607cadacbdd22ebde7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17405
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-11-15 13:09:08 +01:00
Furquan Shaikh bce8bb6e6c google/chromeec: Add elog events for recovery mode switches
BUG=chrome-os-partner:59352
BRANCH=None
TEST=Verified eventlog on reef

0 | 2016-11-12 19:49:25 | Log area cleared | 4088
1 | 2016-11-12 19:49:25 | Kernel Event | Clean Shutdown
2 | 2016-11-12 19:49:25 | ACPI Enter | S5
3 | 2016-11-12 19:49:39 | System boot | 365
4 | 2016-11-12 19:49:39 | EC Event | Power Button
5 | 2016-11-12 19:49:45 | Chrome OS Recovery Mode | Recovery Button
Pressed
6 | 2016-11-12 19:49:45 | Chrome OS Developer Mode
7 | 2016-11-12 19:49:45 | EC Event | Keyboard Recovery
8 | 2016-11-12 19:49:45 | Memory Cache Update | Recovery | Success
9 | 2016-11-12 19:50:46 | System boot | 366
10 | 2016-11-12 19:50:46 | EC Event | Power Button
11 | 2016-11-12 19:50:52 | Chrome OS Recovery Mode | Recovery Button
Pressed
12 | 2016-11-12 19:50:52 | Chrome OS Developer Mode
13 | 2016-11-12 19:50:52 | EC Event | Keyboard Recovery Forced Hardware
Reinit
14 | 2016-11-12 19:50:52 | Memory Cache Update | Recovery | Success
15 | 2016-11-12 19:51:24 | Power Button
16 | 2016-11-12 19:51:24 | ACPI Enter | S5
17 | 2016-11-12 19:51:27 | System boot | 367
18 | 2016-11-12 19:51:27 | EC Event | Power Button
19 | 2016-11-12 19:51:32 | Wake Source | Power Button | 0
20 | 2016-11-12 19:51:32 | ACPI Wake | S5
21 | 2016-11-12 19:51:32 | Chrome OS Developer Mode
22 | 2016-11-12 19:51:32 | Memory Cache Update | Normal | Success

Change-Id: I45dda210cf9d4e5a75404792fcee15b2010787a7
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17394
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-14 20:15:03 +01:00
Furquan Shaikh 626eea2d42 vboot: Add new function for logging recovery mode switches
BUG=chrome-os-partner:59352
BRANCH=None
TEST=Compiles successfully

Change-Id: I87cd675ea45a8b05a178cf64119bf5f9d8d218ca
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17408
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-14 20:13:26 +01:00
Furquan Shaikh 941e27bebb elog: Update event log IDs for EC events
BUG=chrome-os-partner:59352
BRANCH=None
TEST=Compiles successfully

Change-Id: Idf2d377bf4709ea25616adfbde55f39798c0cd39
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17393
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-14 20:12:37 +01:00
Furquan Shaikh b36cb079a5 commonlib: Add new cbmem id for EC_HOSTEVENT
BUG=chrome-os-partner:59352
BRANCH=None
TEST=Compiles successfully.

Change-Id: Ife167bff484ef552bd6cd2e61fdc8291ad6a8acf
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17392
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-14 20:12:10 +01:00
Vadim Bendebury 289ee8f0e9 lib/tpm2: do not create all NVRAM spaces with the same set of attributes
The TPM spaces created by the RO need to have different attributes
depending on the space's use. The firmware rollback counter and MRC
hash spaces are created by the RO code and need to be protected at the
highest level: it should be impossible to delete or modify the space
once the RO exits, and it is how it is done before this patch.

The rest of the spaces should be possible to modify or recreate even
after the RO exits. Let's use different set of NVRAM space attributes
to achieve that, and set the 'pcr0 unchanged' policy only for the
firmware counter and MRC cache spaces.

The definitions of the attributes can be found in "Trusted Platform
Module Library Part 2: Structures", Revision 01.16, section "13.2
TPMA_NV (NV Index Attributes)."

CQ-DEPEND=CL:410127
BRANCH=none
BUG=chrome-os-partner:59651
TEST=verified that the reef system boots fine in both normal and
     recovery modes; using tpmc confirmed that firmware, kernel and
     MRC cache NVRAM spaces are readable in both and writeable only in
     recovery mode.

Change-Id: I1a1d2459f56ec929c9a92b39175888b8d1bcda55
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/17388
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Andrey Pronin <apronin@chromium.org>
2016-11-14 19:11:55 +01:00
Sathyanarayana Nujella c446704e71 soc/intel/apollolake: Increase HEAP_SIZE
Adding both 2-ch & 4-ch DMIC blob causes the below error:
memalign(boundary=8, size=3048): failed: Tried to round up
	free_mem_ptr 7abc48b0 to 7abc5498
but free_mem_end_ptr is 7abc4d70
Error! memalign: Out of memory (free_mem_ptr >= free_mem_end_ptr)

Increased heap size fixes the above issue.

BUG=chrome-os-partner:56918
BRANCH=none
TEST=Compiles successfully for reef

Change-Id: Ic910f169f7ef4bb746cb273e276428713a884227
Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-on: https://review.coreboot.org/17157
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-14 18:13:29 +01:00
Sathyanarayana Nujella 3e0a3fb1c2 soc/intel/apollolake: Add support for DMIC 4ch & 1ch
Add NHLT support for DMIC Quad & Mono channel capture

BUG=chrome-os-partner:56918
BRANCH=none

Change-Id: If630ed53bb2cf00ccc441eb062b2e8c650d3cf01
Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-on: https://review.coreboot.org/17156
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-14 18:12:11 +01:00