Commit Graph

19711 Commits

Author SHA1 Message Date
Martin Roth f924aee3c1 soc/nvidia/tegra210: Remove CONSOLE_SERIAL_TEGRA210_UART_CHOICES
The Kconfig symbol CONSOLE_SERIAL_TEGRA210_UART_CHOICES was attached to
a choice, and isn't used anywhere.  Remove it as unnecessary.

Change-Id: I4efd2e43ac34b266db0d40d1bc8c123bd377b3a2
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/17391
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-11-14 18:10:57 +01:00
Shaunak Saha a012254d01 intel/apollolake: Enable turbo
This patch adds punit initialization code after
FspMemoryInit so that turbo can be initialized after
that.

BUG=chrome-os-partner:58158
BRANCH=None

Change-Id: I4939da47da82b9a728cf1b5cf6d5ec54b4f5b31d
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/17203
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-14 18:10:05 +01:00
Lin Huang a09b338362 soc/rockchip: split edp_enable() function
To avoid garbage display in firmware on warm reset, we need
to enable eDP display in depthcharge instead when the framebuffer is
cleared.
Therefore limit edp_enable() in coreboot to just configure eDP,
and leave enabling the display to depthcharge.

CQ-DEPEND=CL:402071
BUG=chrome-os-partner:58675
BRANCH=none
TEST=Boot from kevin, and display work

Change-Id: I9d937ead33ebba58e33e02fd73b80d6e11bb69aa
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 38b0d18c3fae37dfccb18fe809f763b98703167c
Original-Change-Id: Ibbc283a5892b98f4922f02fd67465fe2e1d01b71
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/402095
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/17207
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-14 18:08:11 +01:00
Sumeet Pawnikar 1d6957e9a9 google/chell : update DPTF policy settings
Fine tuned DPTF policy values for chell device as below,
1. Increase Passive temperature value to 52 degree Celsius for TSR2.
2. Remove charger effect for TSR2.
3. Increase Minimum PowerLimit1 to 3W.
4. Reduce Maximum PowerLimit1 to 6W.

BUG=chrome-os-partner:54718
BRANCH=None.
TEST=Built for chell device.

Change-Id: I46f69e3cd527ea3d28bdd7daa29d91f76770c277
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/17376
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-14 18:07:50 +01:00
Sumeet Pawnikar 8b3004e2fc skylake: Update the thermal time window for throttling action
This patch reduces the thermal time window to 100 milliseconds
for fast throttling action at prochot.

BUG=chrome-os-partner:59397
BRANCH=None.
TEST=Built for skylake platform and verified the thermal time
window value.

Change-Id: If79d213cb8e19277ffdb882267d2f8672df93446
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/17384
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-14 17:20:38 +01:00
Subrata Banik 5b8c4a7bca drivers/pc80/tpm: Select TPM device name based on Kconfig option
Device ID remains same for SLB9670 Infineon TPM 1.1 and TPM 2.0
chip. Hence select based on TPM2 Kconfig option.

BUG=none
BRANCH=none
TEST=Build and boot SKL RVP with SPI TPM 2.0 module

Change-Id: I57e63f2f2899d25ed6b797930fd8bf1d1cdc1b1d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/17374
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-14 17:18:21 +01:00
Naresh G Solanki b5580ad55f intel/kblrvp: Enable TPM
Add choice to build without TPM, TPM 1.2 support or TPM 2.0 support.

Additionally configure lpc clock pad used with LPC TPM & update devicetree.cb.

Change-Id: I1c24fdefa6e73637b3037ecf118559abe5fde300
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/17367
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-11-14 17:17:38 +01:00
Ronald G. Minnich 3d302b03f4 riscv: add a variable to control trap management
This variable can be set in a debugger (e.g. Spike)
to finely control which traps go to coreboot and
which go to the supervisor.

Change-Id: I292264c15f002c41cf8d278354d8f4c0efbd0895
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/17404
Tested-by: build bot (Jenkins)
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2016-11-14 01:09:12 +01:00
Martin Roth 42c1e43cb1 Documentation: Add Kconfig document
Change-Id: I99ca65343d52e99611644c0c65f4b7feb5c58436
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/16947
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins)
2016-11-13 21:41:44 +01:00
Ronald G. Minnich c270335462 riscv: change payload() to pass the config string pointer as arg0
The riscv 1.9 standard defines a textual config string to be passed
to kernels and hypervisors. Change the payload function to pass
this string in a0.

Change-Id: I3be7f1712accf2d726704e4c970f22749d3c3f36
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/17254
Tested-by: build bot (Jenkins)
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2016-11-13 00:16:37 +01:00
Jonathan Neuschäfer 9453c92b99 MAINTAINERS: Add lowrisc files to RISC-V
Change-Id: I8e9ff5821e15cd9a5966927a8cd8bd95f7021d58
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/17402
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-11-12 19:30:26 +01:00
Ronald G. Minnich 574df1ba67 riscv: start to use the configstring functions
These functions will allow us to remove hardcodes,
as long as we can verify the qemu and lowrisc targets
implement the configstring correctly. Hence, for the
most part, we'll start with mainboard changes first.

Define a new config variable, CONFIG_RISCV_CONFIGSTRING,
which has a default value that works on all existing
systems but which can be changed
as needed for a new SOC or mainboard.

Change-Id: I7dd3f553d3e61f1c49752fb04402b134fdfdf979
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/17256
Tested-by: build bot (Jenkins)
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2016-11-12 19:23:22 +01:00
Ronald G. Minnich 04c94ded3a riscv: bring in the configstring parsing functions from UCB
I've tested this with commits to come later.

This is from the lowrisc bbl distribution, 87588c4,
with fixes so it builds.

Change-Id: I87893638872259c94d6972e1971578b633155e7e
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/17255
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-11-12 09:01:14 +01:00
Aaron Durbin 96b3c6f937 drivers/intel/fsp2_0: track end of firmware notifications
The end of firmware notification is currently not being tracked
so it's hard to get good data on how long it takes. Update the
code to provide timestamp data as well as post codes.

BUG=chrome-os-partner:56656

Change-Id: I74c1043f2e72d9d85b23a99b8253ac465f62a7f2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17373
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-11-12 04:07:06 +01:00
Aaron Durbin bf696f5602 soc/intel/apollolake: cache the MMIO BIOS region
If the boot media is memory mapped temporarily mark it as write
protect MTRR type so that memory-mapped accesses are faster.

Depthcharge payload loading was sped up by 75ms using this.

BUG=chrome-os-partner:56656,chrome-os-partner:59682

Change-Id: Iba87a51a05559d81b8e00fa4f6824dacf7a661f5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17372
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-12 04:06:47 +01:00
Aaron Durbin 2bebd7bc93 cpu/x86/mtrr: allow temporary MTRR range during coreboot
Certain platforms have a poorly performing SPI prefetcher so even if
accessing MMIO BIOS once the fetch time can be impacted. Payload
loading is one example where it can be impacted. Therefore, add the
ability for a platform to reconfigure the currently running CPU's
variable MTRR settings for the duration of coreboot's execution.

The function mtrr_use_temp_range() is added which uses the previous
MTRR solution as a basis along with a new range and type to use.
A new solution is calculated with the updated settings and the
original solution is put back prior to exiting coreboot into the OS
or payload.

Using this patch on apollolake reduced depthcharge payload loading
by 75 ms.

BUG=chrome-os-partner:56656,chrome-os-partner:59682

Change-Id: If87ee6f88e0ab0a463eafa35f89a5f7a7ad0fb85
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17371
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-12 04:06:33 +01:00
Aaron Durbin 2b3e0cdfc4 soc/intel/common/lpss_i2c: configure buses by rise/fall times
The default register count calculations are leading to higher
frequencies than expected. Provide an alternative method for
calculating the register counts by utilizing the rise and
fall times of the bus. If the rise time is supplied the
rise/fall time values are used, but the register overrides
take precedence over the rise/fall time calculation.  This
allows platforms to choose whichever method works the best.

BUG=chrome-os-partner:58889

Change-Id: I7747613ce51d8151848acd916c09ae97bfc4b86a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17350
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
2016-11-12 00:19:22 +01:00
Furquan Shaikh 8b5d04e1ab lib/tlcl: Ensure tlcl library is initialized only once
Since tlcl library is used other than just vboot driver, ensure that the
library is initialized only once per stage.

BUG=chrome-os-partner:59355
BRANCH=None
TEST=Verified in recovery mode on reef, tlcl library is initialized only
once in romstage.

Change-Id: I6245fe9ed34f5c174341b7eea8db456b45113287
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17364
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-11 22:15:57 +01:00
Matt DeVillier ffae746c37 samsung/stumpy: fix power LED operation
commit 80EF7B7 [IT8772F: Clean up it8772f includes and add a LED API]
broke power LED operation when it incorrectly transferred
values from the old function (it8772f_gpio_setup) to the new one (
it8772f_gpio_led). Restore the correct values so power LED illuminates
when powered on.

Change-Id: I99a38351bb52063fafa7436e6397a8da7fc1e952
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/17266
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-11 20:24:06 +01:00
Wisley Chen 62d81a0fcc mainboard/google/snappy: Configure PERST pin
Configure GPIO 122 as PERST. This is to assert WiFi PERST
during s0ix entry.

BUG=chrome-os-partner:59034
BRANCH=master
TEST=emerge-snappy coreboot chromeos-bootimage

Change-Id: If2528632fe65c3ed1af19b2ce6f99e8be0cd1ad9
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/17356
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-11 20:23:50 +01:00
Naresh G Solanki 102efd359b kblrvp: Add support for Hynix memory
Add support for hynix memory variant of RVP3.

Change-Id: Ic1f8630b36eb131b70c5e3b620957d9602da11ee
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/17339
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-11 20:16:17 +01:00
Aamir Bohra 6fed46805e mainboard/intel/kblrvp: Add support to read board ID from EC
Add a function to identify an Intel RVP board by querying EC

Change-Id: I21337000827639fb8f22c5ee9bc5d86f1ebe1e74
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/17283
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-11 20:15:00 +01:00
Vadim Bendebury 673a2663a9 src/vboot: mark factory_initialze_tpm() as static
This function is not used anywhere else in the code.

BRANCH=none
BUG=none
TEST=reef and kevin boards (using tpm1.2 and tpm2.0 respectively)
     build successfully.

Change-Id: Ifcc345ae9c22b25fdcfc2e547e70766021d27e32
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/17387
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
2016-11-11 18:53:33 +01:00
Kyösti Mälkki 39915bc290 intel cache-as-ram: Unify stack setup
No need to have %ebx reserved here.

Change-Id: I9fe9292ddc610079b876019a71c69af5b1bcf2a2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17357
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-11 18:52:09 +01:00
Kyösti Mälkki a4ffe9dda0 intel post-car: Separate files for setup_stack_and_mtrrs()
Have a common romstage.c file to prepare CAR stack guards.

MTRR setup around cbmem_top() is somewhat northbridge specific,
place stubs under northbridge for platrform that will move
to RELOCATABLE_RAMSTAGE.

Change-Id: I3d4fe4145894e83e5980dc2a7bbb8a91acecb3c6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15762
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-11 18:43:10 +01:00
Kyösti Mälkki 9b9915284f intel/sandybridge: Use common ACPI S3 recovery
Fix regression, S3 resume not working on sandy/ivy after commit
   9d6f365 ACPI S3: Remove HIGH_MEMORY_SAVE where possible

There is some 20ms delay with ACPI S3 wakeup time due to MTRR setup
being done after the backup copy. Moving to RELOCATABLE_RAMSTAGE fixes
this delay by removing need of this backup entirely.

Change-Id: Ib72ff914f5dfef8611f5f6cf9687495779013b02
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15248
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-11 18:42:07 +01:00
Wisley Chen 5ecc41b0c9 google/snappy: update timing of sdmode toggling
Maxim98357a speaker amp requires BCLK & SFRM to be active
and stable before it is unmuted. If there is a BLCK and no
SFRM, it results in a pop sound.

sdmode_delay property already exists which facilitates this
configuration. This patch updates "sdmode_delay" to avoid
pop sound.

BUG=chrome-os-partner:59034
BRANCH=master
TEST=emerge-snappy coreboot chromeos-bootimage

Change-Id: Ic9095ae6812ba822c760229e69f5b27c6c244cdf
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/17361
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-11 16:14:43 +01:00
Wisley Chen 232d31899b mainboard/google/snappy: Set PL1 override to 12000mW
Snappy is using APL SoC SKU's with 6W TDP max. As Reef,
the energy calculation is wrong with the current VR solution.
Experiments show that SoC TDP max (6W) can be reached
when RAPL PL1 is set to 12W.
Therefore, we've inserted 12W override after reading the fused value (6W)
so that the system can reach the right performance level.

BUG=chrome-os-partner:59034
BRANCH=master
TEST=emerge-snappy coreboot chromeos-bootimage

Change-Id: Idd702077cd05e2b43823542cb804b2d4b42f7116
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/17362
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-11 16:14:24 +01:00
Aaron Durbin 4668ba77ea soc/intel/common/lpss_i2c: simplify API and use common config structure
The apollolake and skylake had duplicate stanzas of code for
initializing the i2c buses. Additionally, they also had very
similar structures for providing settings for the i2c speed
control. Introduce a new struct lpss_i2c_bus_config and
utilize it in both apollolake and skylake thereby removing
the need for SoC-specific structres. The new structure is
used for initializing a bus fully as the lpss i2c API is
simplified in that lpss_i2c_init() is only required to be
called. The struct lpss_i2c_bus_config structure is passed
in for both initializing and filling in the SSDT information.
The formerly exposed functions are made static to reduce the
external API exposure.

BUG=chrome-os-partner:58889

Change-Id: Ib4fa8a7a4de052da75c778a7658741a5a8e0e6b9
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17348
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-11-11 03:11:45 +01:00
Aaron Durbin ed14a4e0df soc/intel/skylake: move i2c voltage config to own variable
In preparation of merging the lpss i2c config structures on
apollolake and skylake move the i2c voltage variable to its
own field. It makes refactoring things easier, and then there's
no reason for a separate SoC specific i2c config structure.

BUG=chrome-os-partner:58889

Change-Id: Ibcc3cba9bac3b5779351b673bc0cc7671d127f24
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17347
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-11-11 03:11:31 +01:00
Furquan Shaikh ce21151a1c mainboard/google/reef: Add digitizer device to devicetree
BUG=chrome-os-partner:56246
BRANCH=None
TEST=Verified kernel is able to talk to the device. Even without the
digitizer, no issues observed with the kernel.

Change-Id: I894a5f4cd8f6a51e641a2c8f7b1f682ab76712ae
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17343
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-11-10 20:40:35 +01:00
Furquan Shaikh ee019d016d mainboard/google/reef: Tune digitizer I2C frequency to 400kHz
This brings the I2C frequency down to 400kHz which is spec for fast
I2C.

BUG=chrome-os-partner:56246
BRANCH=None
TEST=Verified frequency in kernel.

Change-Id: Ib83c57eec8644903cb9c4b2ab50c94038eb690c1
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17342
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-10 20:40:19 +01:00
Furquan Shaikh 73edd2b7c0 drivers/i2c/wacom: Make the driver more generic
Wacom I2C driver can be used by devices other than
touchscreen. e.g. digitizer. So there is no need to name the driver
with touchscreen specific attributes. Only a separate descriptor name
is required that needs to be set by mainboard correctly.

BUG=chrome-os-partner:56246
BRANCH=None
TEST=Compiles successfully.

Change-Id: I0d32a4adae477373b3f4c5f3abbe188860701194
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17341
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-10 20:40:06 +01:00
Naresh G Solanki 5a08fb2203 intel/kblrvp: Program I/O expander
Program I/O expander connected on I2C bus 4

Change-Id: I1a431f50e7b06446399a7d7cb9490615818147e7
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/17338
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-10 20:11:40 +01:00
Furquan Shaikh 2db5bacd90 drivers/intel/fsp2_0: Add support for recovery MRC hash space in TPM
This space is read/updated only in recovery mode.
1. During read phase, verify if the hash of MRC data read from
RECOVERY_MRC_CACHE matches the hash stored in TPM.
2. During update phase, calculate hash of training data returned by MRC
and save it in TPM.

BUG=chrome-os-partner:59355
BRANCH=None
TEST=Verified MRC data hash comparison and update operation on reef.

Change-Id: Ifcbbf1bd22033767625ec55b659e05fa7a7afc16
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17274
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-10 18:10:54 +01:00
Furquan Shaikh b038f41420 vboot: Add support for recovery hash space in TPM
1. Add a new index for recovery hash space in TPM - 0x100b
2. Add helper functions to read/write/lock recovery hash space in TPM
3. Add Kconfig option that can be selected by mainboards that want to
define this space.
4. Lock this new space while jumping from RO to RW.

BUG=chrome-os-partner:59355
BRANCH=None
TEST=Verified use of recovery hash space on reef.

Change-Id: I1cacd54f0a896d0f2af32d4b7c9ae581a918f9bb
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17273
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-10 18:10:42 +01:00
Antonello Dettori 1232666b6f mainboard/thomson/ip1000: transition away from device_t
Replace the use of the old device_t definition inside
mainboard/thomson/ip1000.

Change-Id: Id7b979d2539d4a80609a60464527939c4d449822
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/17308
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-10 17:00:59 +01:00
Antonello Dettori c8a5aa5c3a mainboard/supermicro/h8qme_fam10: transition away from device_t
Replace the use of the old device_t definition inside
mainboard/supermicro/h8qme_fam10.

Change-Id: Ia03c205ce498eadf8a34749a6a21fb2d0b29c840
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/17306
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-10 17:00:01 +01:00
Antonello Dettori 6fec83a2f9 mainboard/supermicro/h8qgi: transition away from device_t
Replace the use of the old device_t definition inside
mainboard/supermicro/h8qgi.

Change-Id: I6cf123272283edbf89e854e4aa1a15a2d566133e
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/17305
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-10 16:59:13 +01:00
Antonello Dettori 0bcd297d93 mainboard/roda/rk9: transition away from device_t
Replace the use of the old device_t definition inside
mainboard/roda/rk9.

Change-Id: I56fec2a2814ee4b91b11f71dbdca1271792cd0e5
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/17302
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-10 16:57:06 +01:00
Antonello Dettori 63028fd29d mainboard/roda/rk886ex: transition away from device_t
Replace the use of the old device_t definition inside
mainboard/roda/rk886ex.

Change-Id: I2e88adc444dbbde7a4344829d7bd5a6c9e1f7531
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/17301
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-10 16:56:30 +01:00
Antonello Dettori 8493b25357 mainboard/rca/rm4100: transition away from device_t
Replace the use of the old device_t definition inside
mainboard/rcs/rm4100.

Change-Id: I8b242eefe796cd93337177fc694ea42c57c53f08
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/17300
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-10 16:55:42 +01:00
Kevin Chiu c4943d86b0 mainboard/google/pyro: Set PL1 override to 12000mW
Pyro is using APL SoC SKU's with 6W TDP max. As Reef,
the energy calculation is wrong with the current VR solution.
Experiments show that SoC TDP max (6W) can be reached
when RAPL PL1 is set to 12W.
Therefore, we've inserted 12W override after reading the fused value (6W)
so that the system can reach the right performance level.

BUG=chrome-os-partner:58112
BRANCH=master
TEST=emerge-pyro coreboot chromeos-bootimage
Change-Id: I6de22d7b2d107f3d26ecfadd4e0904e68318e656
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/17335
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-10 16:52:16 +01:00
Kevin Chiu 961d6d45a6 google/pyro: Tune i2c frequency to 400 Khz
tune i2c devices clk for pyro:
I2C0: audio da7219
I2C2: TPM H1
I2C3: wacom touchscreen
I2C4: elan touchpad

BUG=chrome-os-partner:58881
BRANCH=master
TEST=emerge-pyro coreboot chromeos-bootimage
Change-Id: If3c92ed260277c27a94d2fcf7883e9441519e40e
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/17331
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-10 16:50:48 +01:00
Kevin Chiu 49ef5aa99b google/pyro: update timing of sdmode toggling
Maxim98357a speaker amp requires BCLK & SFRM to be active
and stable before it is unmuted. If there is a BLCK and no
SFRM, it results in a pop sound.

sdmode_delay property already exists which facilitates this
configuration. This patch updates "sdmode_delay" to avoid
pop sound.

BUG=chrome-os-partner:58112
BRANCH=master
TEST=emerge-pyro coreboot chromeos-bootimage
Change-Id: I5aee41957c9de7a05f962d3ede74efc6998a78fc
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/17336
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-10 16:48:59 +01:00
Kevin Chiu f5fb219f0f mainboard/google/pyro: Configure PERST pin
Configure GPIO 122 as PERST. This is to assert WiFi PERST
during s0ix entry.

BUG=chrome-os-partner:58112
BRANCH=master
TEST=emerge-pyro coreboot chromeos-bootimage
Change-Id: Id760251a1b037feb62ec43199a145e407b074769
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/17334
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-10 16:48:22 +01:00
Antonello Dettori 82fcc1afa1 mainboard/kontron/ktqm77: transition away from device_t
Replace the use of the old device_t definition inside
mainboard/kontron/ktqm77.

Change-Id: I47763d1e2bfeee6366ce24b20d874adf7c6f65be
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/17299
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-11-10 00:58:40 +01:00
Furquan Shaikh 06eee265c2 3rdparty/vboot: update to latest master
Require new recovery reason for rec hash space lock failure in RO.

Change-Id: I606d1a1f51a3a4c127b2933f6fb00ba2ec4885fc
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17340
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-11-10 00:57:27 +01:00
Furquan Shaikh 4b2fed50ed antirollback: Sync TPM space indices with vboot library
BUG=chrome-os-partner:59355
BRANCH=None
TEST=Compiles successfully for reef.

Change-Id: I27f2e10556214598d479e4a84e8949465e7da7d6
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17272
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-10 00:56:19 +01:00
Furquan Shaikh fb81474aa5 TPM: Add TPM driver files to romstage
This driver is required for reading and updating TPM space for recovery
MRC data hash in romstage.

BUG=chrome-os-partner:59355
BRANCH=None
TEST=Compiles successfully for reef.

Change-Id: I8edb7af13285a7a192e3d55fc6a11cfe12654bf9
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17270
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-11-10 00:56:04 +01:00