idftool was failing to add the ME blobs into the output image in case
the blob size does not exactly match the size allocated for it in the
flashrom structure.
It is difficult to set the field in the structure to exactly match the
size (for some reason Intel flash tool fails to insert the correct
size even when given the exact ME blob). On the other hand there is no
harm in using am ME blob smaller than the allocated size, this change
modifies the tool building the image to allow for smaller components.
Change-Id: I1b04f90051b91157391943c9bad0eb06dd297431
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/751
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Future CPUs will require TSEG use for SMM
Change-Id: I1432569ece4371d6e12c997e90d66c175fa54c5c
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: http://review.coreboot.org/766
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This avoids using EBX and instead uses EDI where possible,
and ESI when necessary to get the EBX value out.
This allows me to enable -fpic for SMM TSEG code.
Also add a new CPUID extended function to query with ECX set.
Change-Id: I10dbded3f3ad98a39ba7b53da59af6ca3145e2e5
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: http://review.coreboot.org/764
Tested-by: build bot (Jenkins)
Reviewed-by: Mathias Krause <minipli@googlemail.com>
This change makes significant changes to cbmem.py to make it use the
coreboot tables to find the memory console and timestamp areas instead
of looking for the in memory table TOC structure. That appears to be
more robust and gets cbmem.py working again after some unrelated
changes that affected memory layout.
It also introduces some small infrastructure to make accessing C style
structures in physical memory easier and more transparent.
Change-Id: I51833055a50c2d76423520ba6e059bf8fc50adea
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: http://review.coreboot.org/762
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
It's not used on any board supported by coreboot but has been
detected at run time since ages. No new boards (since 2000?)
are using the CONF2 method, so it is unlikely we ever have to
turn this on for a board.
Change-Id: I17df94a8a77b9338fde10a6b114b44d393776e66
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/758
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This adds a number of timestamps in ramstage and romstage
so we can figure out where execution time goes.
Change-Id: Iea17c08774e623fc1ca3fa4505b70523ba4cbf01
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/749
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
It looks like the cbfstool utility generates the output file even when
it fails to generate it properly. This causes make, if started second
time in a row, after cbfstool failure, to continue beyond the point of
failure (as the corrupted output file is present in the output tree,
the second make invocation presumes that it is valid, as it is newer
than the dependencies).
The output file should be created only when successful, in an atomic
operation. There could be other places in the make system which
require a similar fix, this needs to be investigated further.
Change-Id: I7c17f033ee5937eb712b1a594122430cee5c9146
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/750
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
and initialize the TPM on S3 resume
This patch integrates the TPM driver and runs TPM resume upon an ACPI S3
resume without including any other parts of vboot.
We could link against vboot_fw.a but it is compiled with u-boot's CFLAGS
(that are incompatible with coreboot's) and it does a lot more than we
want it to do.
Change-Id: I000d4322ef313e931e23c56defaa17e3a4d7f8cf
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/731
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
... and hook it up in Kconfig. More code to come.
Change-Id: I24542d8ef97e2bce112c3aface681ceeb1a7c061
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/813
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
The cbmem console structure and car global data are put in their own section,
with the cbmem console coming after the global data. These areas are linked
to be where CAR is available and at the very bottom of the stack.
There is one shortcoming of this change:
The section created by this change needs to be stripped out by the Makefile
since leaving it in confuses cbfstool when it installs the stage in the image.
I would like to make the tools link those symbols at the right location but
leave allocation of that space out of the ELF.
Change-Id: Iccfb99b128d59c5b7d6164796d21ba46d2a674e0
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: http://review.coreboot.org/727
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Use an int in CAR global data to store whether or not the OXPCIE serial card
is actually there. Also, time out if the card doesn't show up quickly enough,
don't continue initialization if it's not there, and don't make the
initialization routine default to a card if none is found.
Change-Id: I9c72d3abc6ee2867b77ab2f2180e6f01f647af8c
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: http://review.coreboot.org/728
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
- cash -> Cache
- make the new size of the cbmem console buffer the default
Change-Id: Ia906077257e93622ad56bc54a42f8184ade78b29
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/726
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
These are guarded by individual Kconfig entries. The deprecated
CONFIG_PCIE_TUNING defines have been removed in favor of using specific
config options.
This is the generic half, there is board-specific pieces
still to come that tune before and after ASPM is enabled.
Change-Id: I3fe46282eada67629e9eeeed07e487dff54f2729
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: http://review.coreboot.org/735
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
We need to provide u-boot access to several different CBMEM
sections. To do that, a common coreboot table structure is used,
just different tags match different coreboot table sections.
Also, the code is added to export CBMEM console and MRC cache
addresses through the same mechanism.
Change-Id: I63adb67093b8b50ee61b0deb0b56ebb2c4856895
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/724
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This change exports the timestamp table pointer through coreboot
table to make it possible for u-boot to add timestamps to the
table.
Inclusion of cbmem.h allows to drop external declarations in
coreboot_table.c.
Change-Id: Ia070198cee7a6ffdaeece03d9d15bd91e033b6d1
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/716
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This is a python script which is supposed to run on a target
which is controlled by coreboot. The script examines top of
memory looking for the CBMEM signature at addresses aligned at
128K boundary. Once the script finds the CBMEM, it iterates
through the CBMEM table of contents and parses two entries: the
timestamps and the console log.
This submission is just a template to build upon to create a
utility for displaying CBMEM information while running Linux on
the target.
BUG=chrome-os-partner:4200
TEST=manual
See test description of d81e6b8c8d41f2d6 for test procedure.
Change-Id: Id863a8598eaadc2d20d728f9186843e65cbe6f37
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://gerrit-int.chromium.org/5942
Tested-by: Vadim Bendebury <vbendeb@google.com>
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/723
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
The appropriate Makefiles are modified to include the required
source code in compilation.
Change-Id: I91842b1ba0f89d611d3249b63c020a2713a9124f
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/722
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
The new added code is compiled in when the CBMEM_CONSOLE config
flag is enabled.
Change-Id: Ifd1f492ce6321412a014333babbc5b3f14635988
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/721
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Add CBMEM type for the console buffer section.
Change-Id: I02757c06d71e46af77b02b90b0e6018a37b62406
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/720
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
The CBMEM console driver saves console output in a CBMEM area, which
then is made available to Linux applications for perusing.
There are some system limitations which need to be worked around
to achieve this goal:
- some console traffic is generated before DRAM is initialized,
leave alone CBMEM initialized.
- after the RAM based stage starts, a lot of traffic is generated
before CBMEM is initialized.
As a result, the console log lives in three different places -
the bottom of the cache as RAM space, the CBMEM buffer (where it
is expected to be) and a static buffer used early in the RAM
stage.
When execution starts (in the cache as RAM mode), the console
buffer is allocated at the bottom of the cache as RAM memory
address range. Once DRAM is initialized, the CBMEM structure is
initialized, and then the console buffer contents are copied from
the bottom of the cache as RAM space into the CBMEM area right
before the cache as RAM mode is disabled. The
src/lib/cbmem_console.c:cbmemc_reinit() takes care of the
copying.
At this point the cache as RAM memory is about to be disabled,
but the ROM stage is still going generating console output. To
make sure this output is not lost, cbmemc_reinit() saves the new
buffer address at a fixed location (0x600 was chosen for this),
and the actual "printing" function checks to see if the RAM is
already initialized (the stack is in RAM), and if so, gets the
console buffer pointer from this location instead of using the
cache as RAM address.
When the RAM stage starts, a static buffer is used to store the
console output, as the CBMEM buffer location is not known. Then,
when CBMEM is reinitialized, cbmemc_reinit() again takes care of
the copying.
In case the allocated buffers are not large enough, the excessive
data is dropped, and the copying routine adds some text to the
output buffer to indicate that there has been data lost and how
many characters were dropped.
Change-Id: I8c126e31db6cb2141f7f4f97c5047f39a8db44fc
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/719
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Some experiments have demonstrated that total amount of text
generated by coreboot console when BIOS_SPEW level is enabled
exceeds 40KB.
Console output generated before DRAM is initialized can exceed
2KB. This patch introduces the new configuration option and
assigns adequate default values to cache based and DRAM based
console buffers.
BUG=chrome-os-partner:4200
TEST=manual
. run the following commands in the root directory
cp config.stumpy .config
make menuconfig
. enable the new option (Console->Send console output to a CBMEM buffer)
. save the configuration
Observe the following settings added to the config:
+CONFIG_CONSOLE_CBMEM=y
+CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0xae00
+CONFIG_CONSOLE_CAR_BUFFER_SIZE=0xc00
Change-Id: I209603f516244ae136631e6281ba21ebc6fb1710
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://gerrit-int.chromium.org/5855
Tested-by: Vadim Bendebury <vbendeb@google.com>
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/718
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This change adds 128K to the memory amount set aside for CBMEM in
case the CBMEM console is enabled (to keep the CBMEM 128K byte
aligned). The console buffer size is being set to 64K, which is
enough to accommodate the most verbose coreboot console and
u-boot console.
Change-Id: If583013dfb210de5028d69577675095c6fe2f3ab
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/725
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
These get used later for saving/restoring the MRC scrambler
seed values on each boot.
Change-Id: I6e23f17649bea6d22c4b279ed8d0e5cb6c0885e7
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: http://review.coreboot.org/717
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This fixes loading SeaBIOS when lower memory is reserved.
Change-Id: Idbdcaf95f3307f97307f304d6d677406d059927d
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/732
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
acpi_slp_type is defined in arch/acpi.h, so let's use that instead
of manually spreading extern u8 acpi_slp_type throughout the code.
Change-Id: Ia5eb420364c15ab5a764bc328bbd201ca9cb7837
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/714
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This patch adds code to initialize the time stamp collection
facility in coreboot. It adds a table in the CBMEM section, which
provides the base timer reading value (all other readings are
offsets of this one) and an array of timestamp id/timestamp value
pairs.
Just two values are being added now, this will have to be used
more extensively and also integrated into payloads to provide more
comprehensive boot process time measurements.
Also, since the CBMEM area could already contain a section (from the
previous run, before reset), when processing a section addition
request we should check if a section already exists and return its
address, if so.
Change-Id: I7ed9f5c400bc5432f228348b41fd19a67c36d533
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/713
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
Add a new flag, make it dependent on EARLY_CBMEM_INIT
Change-Id: Idbebcaf298238f31a73e9eb4a9af7b03e857bc74
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/712
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
We want to be able to share data between different phases of firmware
(rom stage/ram stage/payload). Coreboot CBMEM seems an appropriate
location for this data, but normally it is not initialized
until coreboot reaches the ram stage.
This change initializes the CBMEM while still in rom stage in
case CONFIG_EARLY_CBMEM_INIT is set.
Note that there is a discrepancy in how coreboot determines the
size of DRAM at rom and ram stages, get_top_of_ram() is used at
rom stage and is not defined for all platforms. Those platforms
will have to define this function should they enable the
CONFIG_EARLY_CBMEM_INIT flag.
Change-Id: I81691d45e28de59496fb227f2cca4e8c15ece717
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/711
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
We want to be able to communicate information between rom and ram
stages of coreboot. This configuration option will be used to
compile such ability in.
Change-Id: I6736fdc264ecd0b63369b28462d7bb96e4c2b012
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/710
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit adds support for Bifferboard, a 32MB 486 PC
Change-Id: Iad790ebf242ef07bf6298f8e3577783e5e743113
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/810
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This is handy for bifferboard to provide same size as original bootloader.
Change-Id: I179917d8c6354fa55cebdd70918a96cd299c4f3c
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/809
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
So far it just setups things right for Bifferboard. We may change it
in the future to fit other hardware.
Change-Id: I1c4ccff4e47b9cb9e31a738f038fc4f4ebe59087
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/808
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
So far the it just setups the internal resource management for coreboot and
detects the memory size.
Change-Id: I8506390fa6656abfa40d92b8f6ede9b91fe98680
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/807
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Change-Id: I3f3585f15265aa1377f72ba23accf1adb08cb8ac
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/806
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
The coreboot makefile didn't pass the OUT and CC variables to seabios,
so the clean didn't clean anything.
Change-Id: Ieaf0c417d6e5dfb9e0a11df70b03d6313919578b
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/801
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin@se-eng.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
I would prefer to see the exception dump on serial rather than cryptic
GDB protocol.
Change-Id: Ib25513d33e6a31da24586fecb00adb5206bb43bd
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/811
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
Do not use printk on the running thread after it has been sent
the INIT IPI, execution may halt with console spinlock held.
Change-Id: I64608935ea740fb827fa0307442f3fb102de7a08
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/776
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
Only the BSP CPU was able to start its hyper-threading CPU siblings.
When an AP CPU attempts this it calls start_cpu() within start_cpu(),
deadlocking the system with start_cpu_lock.
At the time intel_sibling_init() is run, the BSP CPU is still
walking the cpu_bus linked list in lapic_cpu_init: start_other_cpus().
A sibling CPU appended at the end of this list will get started.
Also fail compile with #error if SERIAL_CPU_INIT==0, as microcode
updates on hyper-threading sibling CPUs must be serialized.
Tested with HT-enabled P4 Xeons on dual-socket604 platform.
Change-Id: I0053f58f49ed604605ce0a55e826d3e1afdc90b6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/775
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
Renamed CONFIG_ROMBASE to ROMSTAGE_BASE and removed it from Kconfig.
Removed no-op calculation in ldscript.
Change-Id: I53d39b60f07db76c8537b3133e59360687b9d4a7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/802
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
There was some corner case where commit-msg failed. Update to
latest upstream version.
Change-Id: I822d6c3f64728de7356401465e00575ac5af8196
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/798
Tested-by: build bot (Jenkins)
Reviewed-by: Bernhard Urban <lewurm@gmail.com>
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
This is developer's testtool. Output from a "rotate ones" -style
pattern helps figure out how DIMM addresses are encoded or routed
on a certain mainboard.
Scattered test should cover every data and address lines on the memory
bus, but is probably limited to the first bank of first DIMM.
Change-Id: I533a7a873bcc434f99e7faed9dc9337d9ab64196
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
[pg: rebase]
Reviewed-on: http://review.coreboot.org/294
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
Changing CMOS value for power-on-after-power-fail was only honored
after reboot, which is counter intuitive (set from "enable" to "disable",
power-off, replug device -> device turns on; and similar cases).
Change-Id: If1d88c1c34c3333b636ed3ec1e1fb9bea394e615
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/444
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
We used a hard coded value for some reason. Don't do that, but use CMOS
instead.
Change-Id: Ib83aa07a3e55bed075150354a060317ebc9d5ba7
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/443
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Stefan Reinauer