Kyösti Mälkki cd7a70f487 soc/intel: Use common romstage code ... This provides stack guards with checking and common entry into postcar. The code in cpu/intel/car/romstage.c is candidate for becoming architectural so function prototype is moved to <arch/romstage.h>. Change-Id: I4c5a9789e7cf3f7f49a4a33e21dac894320a9639 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34893 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2019-08-26 21:08:41 +00:00
..
acpi
acpi_tables.c
board_info.txt
bootblock.c	sb/intel/lynxpoint: Enable LPC/SIO setup in bootblock	2019-04-23 10:12:02 +00:00
cmos.default
cmos.layout	mb/asrock/h81m-hds: Allow "keep state" for power_on_after_fail	2018-12-19 05:26:58 +00:00
data.vbt
devicetree.cb	sb/intel/lynxpoint: Handle H81 only having 6 PCIe root ports	2018-12-28 12:22:35 +00:00
dsdt.asl	cpu/intel/common: Use a common acpi/cpu.asl file	2018-11-30 22:02:35 +00:00
gma-mainboard.ads
gpio.c	mb/asrock/h81m-hds: Move GPIO header to a linked C file	2019-01-03 18:10:27 +00:00
hda_verb.c
Kconfig	intel/haswell: Replace monotonic timer	2019-07-13 17:56:32 +00:00
Kconfig.name
mainboard.c
Makefile.inc	sb/intel/lynxpoint: Enable LPC/SIO setup in bootblock	2019-04-23 10:12:02 +00:00
romstage.c	soc/intel: Use common romstage code	2019-08-26 21:08:41 +00:00