Lijian Zhao 031020e431 soc/intel/cannonlake: Correct PMC/GPIO routing information ... PMC and GPIO DWx definition is not identical, hence update that to correct information. For cannonlake lp PCH, GPIO group C, group E and group GPD is different for PMC GPIO_CFG and GPIO MISCCFG. Also add function call to set up GPE routing in bootblock stage. TEST=Boot up into OS, and manually check PMC GPE status Change-Id: I1edb83edabc72e8a762b129cf51dcd936cd37ddf Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/22908 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>		2018-01-05 20:44:15 +00:00
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apollolake	soc/intel/{apollolake, cannonlake, common, skylake}: Add _soc_ prefix in weak function	2017-12-23 05:23:09 +00:00
baytrail	drivers/mrc_cache: move mrc_cache support to drivers	2017-12-17 18:29:41 +00:00
braswell	drivers/mrc_cache: move mrc_cache support to drivers	2017-12-17 18:29:41 +00:00
broadwell	drivers/mrc_cache: move mrc_cache support to drivers	2017-12-17 18:29:41 +00:00
cannonlake	soc/intel/cannonlake: Correct PMC/GPIO routing information	2018-01-05 20:44:15 +00:00
common	soc/intel/common/block/gspi: Add SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2	2017-12-23 09:17:54 +00:00
denverton_ns	soc/intel/denverton_ns: Add Denverton-AD system agent id	2017-12-20 16:40:53 +00:00
fsp_baytrail	soc/intel/fsp_baytrail: remove nvm headers and code	2017-12-17 18:29:08 +00:00
fsp_broadwell_de	Constify struct cpu_device_id instances	2017-11-23 05:00:17 +00:00
quark	soc/intel/quark/spi: Correct conversion specifier	2017-11-03 15:22:06 +00:00
sch
skylake	soc/intel/skylake: Add device setting for sata power optimization	2018-01-02 07:39:12 +00:00
Kconfig