Elyes HAOUAS 985821c4f2 cpu/intel/socket_LGA775: Increase DCACHE_RAM_SIZE ... Increase DCACHE_RAM_SIZE to 32kB and remove "NO_CBFS_MCACHE". It’s quite safe to increase DCACHE_RAM_SIZE. All LGA775 targets should have at least 256K L2 cache. That is plenty for XIP RO cache of bootblock + romstage and a 32K CAR. Change-Id: I393b2727bd90a990c3108a4dbead62b17d7fc531 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49505 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>		2021-01-21 09:08:14 +00:00
..
a88xm-e	mb/**/cmos.layout: Indent everything with tabs	2020-11-23 09:56:20 +00:00
am1i-a	mb/**/cmos.layout: Indent everything with tabs	2020-11-23 09:56:20 +00:00
f2a85-m	mb/**/cmos.layout: Indent everything with tabs	2020-11-23 09:56:20 +00:00
h61m-cs	mb/x/acpi_tables: Rename to mainboard_fill_gnvs()	2021-01-10 11:29:10 +00:00
maximus_iv_gene-z	mb/x/acpi_tables: Rename to mainboard_fill_gnvs()	2021-01-10 11:29:10 +00:00
p2b	mainboard/*/*/dsdt.asl: Make DefinitionBlock's AMLFileName uniform	2020-10-13 18:27:13 +00:00
p5gc-mx	cpu/intel/socket_LGA775: Increase DCACHE_RAM_SIZE	2021-01-21 09:08:14 +00:00
p5qc	mainboards: Drop GNVS cmap and cmbp	2021-01-20 09:25:08 +00:00
p5ql-em	mainboards: Drop GNVS cmap and cmbp	2021-01-20 09:25:08 +00:00
p5qpl-am	mainboards: Drop GNVS cmap and cmbp	2021-01-20 09:25:08 +00:00
p8h61-m_lx	mb/x/acpi_tables: Rename to mainboard_fill_gnvs()	2021-01-10 11:29:10 +00:00
p8h61-m_lx3_r2_0	ACPI: Select ACPI_SOC_NVS only where suitable	2021-01-18 07:21:34 +00:00
p8h61-m_pro	ACPI: Select ACPI_SOC_NVS only where suitable	2021-01-18 07:21:34 +00:00
p8z77-m_pro	ACPI: Select ACPI_SOC_NVS only where suitable	2021-01-18 07:21:34 +00:00
p8z77-v_lx2	ACPI: Select ACPI_SOC_NVS only where suitable	2021-01-18 07:21:34 +00:00
Kconfig
Kconfig.name