03df460af5
A new board revision is making use of two previously unused GPIOs to drive BOOT/RESET pins to an on-board MCU. The reset pin is open drain so it is set as input by default, and the boot pin is driven low by default. Since these are UART0 pins they also need to be set up again after executing FSP-S as it will change them back to native mode pins. BUG=b:36025702 BRANCH=none TEST=manual testing on reworked board, toggling GPIOs to put the MCU into programming mode. Change-Id: Id6f0ef2f863bc1e873b58e344446038786b59d25 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18661 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) |
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| .. | ||
| acpi | ||
| spd | ||
| acpi_tables.c | ||
| board_info.txt | ||
| boardid.c | ||
| bootblock.c | ||
| chromeos.c | ||
| chromeos.fmd | ||
| devicetree.cb | ||
| dsdt.asl | ||
| ec.c | ||
| ec.h | ||
| gpio.h | ||
| Kconfig | ||
| Kconfig.name | ||
| mainboard.c | ||
| Makefile.inc | ||
| ramstage.c | ||
| romstage.c | ||
| smihandler.c | ||