Mario Scheithauer f5a48989b4 soc/intel/elkhartlake: Make PCIe root port max payload size configurable ... The data payload size of PCIe root ports can be set to either 128 (default) or 256 bytes. A bigger payload size can improve PCIe data throughput on the given port. FSP-S provides a parameter to configure this value. This patch provides a chip config so that this FSP parameter can be set as needed in the devicetree on mainboard level. Change-Id: I5798a72adaa8089dda0b4bc12266b5a235ed4aa3 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75126 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>		2023-05-24 11:25:24 +00:00
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amd	soc/amd/mendocino: Unmap hash table after usage	2023-05-22 12:49:27 +00:00
cavium	soc/cavium/cn81xx: Use correct size for MPIDR_EL1 register	2023-05-13 17:22:16 +00:00
example/min86
intel	soc/intel/elkhartlake: Make PCIe root port max payload size configurable	2023-05-24 11:25:24 +00:00
mediatek	soc/mediatek/mt8195/apusys_devapc.c: Fix unsigned comparison	2023-05-13 09:30:21 +00:00
nvidia	treewide: stop calling custom TPM log "TCPA"	2023-01-11 16:00:55 +00:00
qualcomm	soc/qualcomm/sc7180: Fix set but unused variables	2023-05-12 16:36:44 +00:00
rockchip	cbmem_top_chipset: Change the return value to uintptr_t	2022-11-18 16:00:45 +00:00
samsung	treewide: Fix old-style declarations	2023-01-17 04:23:49 +00:00
sifive/fu540	cbmem_top_chipset: Change the return value to uintptr_t	2022-11-18 16:00:45 +00:00
ti	src/soc/ti: Remove unnecessary space after casts	2022-11-22 13:42:28 +00:00
ucb/riscv	cbmem_top_chipset: Change the return value to uintptr_t	2022-11-18 16:00:45 +00:00