Arthur Heymans 051ee4e3ad soc/intel/xeon_sp: Lock down DMICTL ... This is required for CBnT. Change-Id: I290742c163f5f067c8d529ddca8e2d8572ab6e6a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47449 Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2020-11-20 00:47:05 +00:00
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amd	include/device/pci_ids: add model number to ATI GPU and HDA controller	2020-11-19 22:02:09 +00:00
cavium	soc/cavium: Drop unneeded empty lines	2020-09-22 17:14:49 +00:00
example	x86: Add a minimal example SoC along with a board	2020-10-30 21:34:18 +00:00
intel	soc/intel/xeon_sp: Lock down DMICTL	2020-11-20 00:47:05 +00:00
mediatek	mb/google/asurada: Implement enable_regulator and regulator_is_enabled	2020-11-18 06:13:26 +00:00
nvidia	soc/nvidia/tegra124/include/soc/clk_rst.h: Remove extra tab	2020-11-09 10:31:32 +00:00
qualcomm	src: Add missing 'include <console/console.h>'	2020-11-17 09:50:24 +00:00
rockchip	src: Change bare 'unsigned' to 'unsigned int'	2020-11-16 11:03:16 +00:00
samsung	src/soc/samsung: Move common headers to "common/include/soc"	2020-10-19 07:11:32 +00:00
sifive	include/console/uart: make index parameter unsigned	2020-09-12 14:59:33 +00:00
ti	include/console/uart: make index parameter unsigned	2020-09-12 14:59:33 +00:00
ucb	soc/ucb/riscv: Add chip_operations stub	2020-05-28 09:30:35 +00:00