b7b5115360
FSP-S hides the PMC from the PCI bus when it runs, but there are still initialization steps coreboot programs for the PMC. Therefore, change all of the cannonlake mainboards to set the PMC as hidden in the devicetree, which means the device will be skipped during enumeration, but device callbacks are still issued as if the device were enabled. TEST=Ran full patch train on google/dratini, disassembled SSDT and the PEPD device matches what is in pep.asl. Also verified via dmesg that the INT33A1 device is still initialized by the kernel. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ib4a20ce9075ce7653388a5d3e281fe774bf89355 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56008 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> |
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| .. | ||
| spd | ||
| variants | ||
| board_info.txt | ||
| bootblock.c | ||
| chromeos-hatch-16MiB.fmd | ||
| chromeos-hatch-32MiB.fmd | ||
| chromeos-puff-16MiB.fmd | ||
| chromeos-puff-32MiB.fmd | ||
| chromeos.c | ||
| dsdt.asl | ||
| ec.c | ||
| Kconfig | ||
| Kconfig.name | ||
| Makefile.inc | ||
| ramstage.c | ||
| romstage_spd_cbfs.c | ||
| romstage_spd_smbus.c | ||
| smihandler.c | ||