aa902036d0
The wake source macro for GPE events was using 'GPIO'. However, current usage is really all GPEs. Therefore, provide clarity in the naming in order to allow for proper GPIO wake events that are separate from the ACPI GPE block. BUG=b:159947207 Change-Id: I27d0ab439c58b1658ed39158eddb1213c24d328f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44527 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
129 lines
3.4 KiB
C
129 lines
3.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <bootstate.h>
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#include <console/console.h>
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#include <stdint.h>
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#include <elog.h>
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#include <intelblocks/pmclib.h>
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#include <soc/pci_devs.h>
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#include <soc/pm.h>
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static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start)
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{
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int i;
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gpe0_sts &= gpe0_en;
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for (i = 0; i <= 31; i++) {
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if (gpe0_sts & (1 << i))
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elog_add_event_wake(ELOG_WAKE_SOURCE_GPE, i + start);
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}
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}
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static void pch_log_wake_source(struct chipset_power_state *ps)
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{
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/* Power Button */
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if (ps->pm1_sts & PWRBTN_STS)
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elog_add_event_wake(ELOG_WAKE_SOURCE_PWRBTN, 0);
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/* RTC */
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if (ps->pm1_sts & RTC_STS)
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elog_add_event_wake(ELOG_WAKE_SOURCE_RTC, 0);
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/* PCI Express (TODO: determine wake device) */
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if (ps->pm1_sts & PCIEXPWAK_STS)
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elog_add_event_wake(ELOG_WAKE_SOURCE_PCIE, 0);
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/* PME (TODO: determine wake device) */
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if (ps->gpe0_sts[GPE_STD] & PME_STS)
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elog_add_event_wake(ELOG_WAKE_SOURCE_PME, 0);
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/* Internal PME (TODO: determine wake device) */
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if (ps->gpe0_sts[GPE_STD] & PME_B0_STS)
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elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0);
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/* SMBUS Wake */
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if (ps->gpe0_sts[GPE_STD] & SMB_WAK_STS)
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elog_add_event_wake(ELOG_WAKE_SOURCE_SMBUS, 0);
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/* Log GPIO events in set 1-3 */
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pch_log_gpio_gpe(ps->gpe0_sts[GPE_31_0], ps->gpe0_en[GPE_31_0], 0);
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pch_log_gpio_gpe(ps->gpe0_sts[GPE_63_32], ps->gpe0_en[GPE_63_32], 32);
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pch_log_gpio_gpe(ps->gpe0_sts[GPE_95_64], ps->gpe0_en[GPE_95_64], 64);
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/* Treat the STD as an extension of GPIO to obtain visibility. */
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pch_log_gpio_gpe(ps->gpe0_sts[GPE_STD], ps->gpe0_en[GPE_STD], 96);
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}
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static void pch_log_power_and_resets(struct chipset_power_state *ps)
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{
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/* Thermal Trip */
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if (ps->gblrst_cause[0] & GBLRST_CAUSE0_THERMTRIP)
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elog_add_event(ELOG_TYPE_THERM_TRIP);
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/* CSME-Initiated Host Reset with power down */
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if (ps->hpr_cause0 & HPR_CAUSE0_MI_HRPD)
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elog_add_event(ELOG_TYPE_MI_HRPD);
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/* CSME-Initiated Host Reset with power cycle */
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if (ps->hpr_cause0 & HPR_CAUSE0_MI_HRPC)
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elog_add_event(ELOG_TYPE_MI_HRPC);
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/* CSME-Initiated Host Reset without power cycle */
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if (ps->hpr_cause0 & HPR_CAUSE0_MI_HR)
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elog_add_event(ELOG_TYPE_MI_HR);
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/* PWR_FLR Power Failure */
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if (ps->gen_pmcon_a & PWR_FLR)
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elog_add_event(ELOG_TYPE_POWER_FAIL);
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/* SUS Well Power Failure */
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if (ps->gen_pmcon_a & SUS_PWR_FLR)
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elog_add_event(ELOG_TYPE_SUS_POWER_FAIL);
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/* TCO Timeout */
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if (ps->prev_sleep_state != ACPI_S3 &&
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ps->tco2_sts & TCO_STS_SECOND_TO)
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elog_add_event(ELOG_TYPE_TCO_RESET);
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/* Power Button Override */
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if (ps->pm1_sts & PRBTNOR_STS)
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elog_add_event(ELOG_TYPE_POWER_BUTTON_OVERRIDE);
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/* RTC reset */
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if (ps->gen_pmcon_b & RTC_BATTERY_DEAD)
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elog_add_event(ELOG_TYPE_RTC_RESET);
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/* Host Reset Status */
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if (ps->gen_pmcon_a & HOST_RST_STS)
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elog_add_event(ELOG_TYPE_SYSTEM_RESET);
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/* ACPI Wake Event */
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if (ps->prev_sleep_state != ACPI_S0)
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elog_add_event_byte(ELOG_TYPE_ACPI_WAKE, ps->prev_sleep_state);
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}
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static void pch_log_state(void *unused)
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{
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struct chipset_power_state *ps = pmc_get_power_state();
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if (!ps) {
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printk(BIOS_ERR, "chipset_power_state not found!\n");
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return;
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}
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/* Power and Reset */
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pch_log_power_and_resets(ps);
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/* Wake Sources */
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if (ps->prev_sleep_state > ACPI_S0)
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pch_log_wake_source(ps);
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}
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BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, pch_log_state, NULL);
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void elog_gsmi_cb_platform_log_wake_source(void)
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{
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struct chipset_power_state ps;
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pmc_fill_pm_reg_info(&ps);
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pch_log_wake_source(&ps);
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}
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