Andrey Petrov 0910f4e76f soc/intel/apollolake: Disable HECI2 device reset on S3 resume ... Converged Security Engine (CSE) has a secure variable storage feature. However, this storage is expected to be reset during S3 resume flow. Since coreboot does not use secure storage feature, disable HECI2 reset request. This saves appr. 130ms of resume time. BUG=chrome-os-partner:56941 BRANCH=none TEST=powerd_dbus_suspend; resume; check time with cbmem -t. Note FspMemoryInit time is not significantly different from normal boot time case. Change-Id: I485a980369c6bd97c43b9e554d65ee89e84d8233 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/16870 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>		2016-10-07 19:14:13 +02:00
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apollolake	soc/intel/apollolake: Disable HECI2 device reset on S3 resume	2016-10-07 19:14:13 +02:00
baytrail	src/soc: Add required space before opening parenthesis '('	2016-08-31 20:09:42 +02:00
braswell	Makefile.inc: Use $(MAINBOARDDIR)	2016-09-04 05:33:25 +02:00
broadwell	Kconfig: Update default hex values to start with 0x	2016-10-02 19:08:15 +02:00
common	lpss_i2c: Add Kconfig option to enable debug	2016-09-14 22:24:06 +02:00
fsp_baytrail	fsp_baytrail: Refactor code for SPI debug messages	2016-09-06 21:17:59 +02:00
fsp_broadwell_de	soc/intel/fsp_broadwell_de/uart: Drop it	2016-09-30 18:18:01 +02:00
quark	soc/intel/quark: Fix FSP 2.0 build	2016-09-30 01:16:51 +02:00
sch	src/soc: Remove unnecessary whitespace before "\n" and "\t"	2016-08-28 18:25:14 +02:00
skylake	soc/intel/skylake: Add config option for Skylake-H Sku support	2016-10-01 22:30:02 +02:00