a8753e9cbb
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 and Purism Librem 13 v1 remain identical. Change-Id: I74b633fb0b012304b5b4bd943272ed82dcb6f7d5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52468 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
65 lines
2.1 KiB
C
65 lines
2.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <bootstate.h>
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#include <console/console.h>
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#include <console/post_codes.h>
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#include <device/pci_ops.h>
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#include <soc/pci_devs.h>
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#include <soc/pch.h>
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#include <soc/systemagent.h>
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/*
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* 16.6 System Agent Configuration Locking
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* "5th Generation Intel Core Processor Family BIOS Specification"
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* Document Number 535094
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* Revision 2.2.0, August 2014
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*
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* To ease reading, first lock PCI registers, then MCHBAR registers.
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* Write the MC Lock register first, since more than one bit gets set.
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*/
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static void broadwell_systemagent_finalize(void)
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{
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struct device *const host_bridge = pcidev_path_on_root(SA_DEVFN_ROOT);
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pci_or_config16(host_bridge, GGC, 1 << 0);
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pci_or_config32(host_bridge, DPR, 1 << 0);
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pci_or_config32(host_bridge, MESEG_LIMIT, 1 << 10);
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pci_or_config32(host_bridge, REMAPBASE, 1 << 0);
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pci_or_config32(host_bridge, REMAPLIMIT, 1 << 0);
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pci_or_config32(host_bridge, TOM, 1 << 0);
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pci_or_config32(host_bridge, TOUUD, 1 << 0);
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pci_or_config32(host_bridge, BDSM, 1 << 0);
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pci_or_config32(host_bridge, BGSM, 1 << 0);
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pci_or_config32(host_bridge, TSEG, 1 << 0);
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pci_or_config32(host_bridge, TOLUD, 1 << 0);
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mchbar_setbits32(0x50fc, 0x8f); /* MC */
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mchbar_setbits32(0x5500, 1 << 0); /* PAVP */
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mchbar_setbits32(0x5880, 1 << 5); /* DDR PTM */
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mchbar_setbits32(0x7000, 1 << 31);
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mchbar_setbits32(0x77fc, 1 << 0);
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mchbar_setbits32(0x7ffc, 1 << 0);
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mchbar_setbits32(0x6800, 1 << 31);
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mchbar_setbits32(0x6020, 1 << 0); /* UMA GFX */
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mchbar_setbits32(0x63fc, 1 << 0); /* VTDTRK */
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/* Read+write the following */
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mchbar_setbits32(0x6030, 0);
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mchbar_setbits32(0x6034, 0);
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mchbar_setbits32(0x6008, 0);
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}
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static void broadwell_finalize(void *unused)
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{
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printk(BIOS_DEBUG, "Finalizing chipset.\n");
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broadwell_systemagent_finalize();
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broadwell_pch_finalize();
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/* Indicate finalize step with post code */
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post_code(POST_OS_BOOT);
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}
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BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, broadwell_finalize, NULL);
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BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, broadwell_finalize, NULL);
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