Subrata Banik 0e2510f616 soc/intel/common/block/cpu: Introduce CAR_HAS_L3_PROTECTED_WAYS Kconfig ... Alder Lake onwards IA SoC to select CAR_HAS_L3_PROTECTED_WAYS from SoC Kconfig and here is modified flow as below: Add new MSR 0xc85 IA32_L3_PROTECTED_WAYS Update eNEM init flow: - Set MSR 0xC85 L3_Protected_ways = (1 << data ways) - 1 Update eNEM teardown flow: - Set MSR 0xC85 L3_Protected_ways = 0x00000 BUG=b:168820083 TEST=Verified filling up the entire cache with memcpy at the beginning itself and then running the entire bootblock, verstage, debug FSP-M without running into any issue. This proves that code caching and eviction is working as expected in eNEM mode. Change-Id: Idb5a9ec74c50bda371c30e13aeadbb4326887fd6 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48344 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>		2021-08-16 05:07:12 +00:00
..
acpi	Move post_codes.h to commonlib/console/	2021-08-04 15:15:51 +00:00
basecode
block	soc/intel/common/block/cpu: Introduce CAR_HAS_L3_PROTECTED_WAYS Kconfig	2021-08-16 05:07:12 +00:00
pch	soc/intel/common: Add InSMM.STS support	2021-06-21 08:26:41 +00:00
fsp_reset.c
hda_verb.c	soc/intel/common/hda_verb.c: Fix up comment style	2021-03-22 12:59:57 +00:00
hda_verb.h
Kconfig.common
Makefile.inc	soc/intel: Remove duplicate call to acpi_wake_source()	2021-01-29 19:35:25 +00:00
mma.c	intel: mma: Use new CBFS API	2021-04-14 01:03:33 +00:00
mma.h	intel: mma: Use new CBFS API	2021-04-14 01:03:33 +00:00
nhlt.c
reset.c
reset.h
smbios.c	device/dram/ddr3: Rename DDR3 SPD memory types	2021-04-05 13:01:37 +00:00
smbios.h
tpm_tis.c
vbt.c
vbt.h