Alexey Buyanov 12016969c5 soc/intel/tigerlake: Rename pch_init() code ... Rename the pch_init function to bootblock_pch_init and romstage_pch_init according to the stage it is defined in. TEST=successfully built and booted TGLRVP Signed-off-by: Alexey Buyanov <alexey.buyanov@intel.com> Change-Id: Ib7450fcdc3024dfb5e375a54f9bdcdca9bc373d8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44051 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>		2020-08-26 07:36:21 +00:00
..
acpi	src/acpi: Drop unneeded empty lines	2020-08-24 09:16:59 +00:00
arch	src/arch: Drop unneeded empty lines	2020-08-24 09:16:19 +00:00
commonlib	src: Remove unused 'include <stdint.h>	2020-07-14 16:11:10 +00:00
console	src: Remove unused 'include <stddef.h>	2020-08-18 12:15:44 +00:00
cpu	Revert "cpu/x86/sipi: Add x86_64 support"	2020-08-24 11:35:31 +00:00
device	{sb/intel/*/azalia.c,device/azalia_device.c}: Reduce differences	2020-08-17 06:58:45 +00:00
drivers	mrc_cache: Move mrc_cache_stash_data to end of file	2020-08-24 23:31:26 +00:00
ec	ec/google/chromeec: Add helper to request AP reset	2020-08-14 08:35:15 +00:00
include	include/imd: Improve API documentation	2020-08-26 07:32:37 +00:00
lib	lib/imd: Prohibit removing imd_entry covering root region	2020-08-26 07:33:13 +00:00
mainboard	mb/google/asurada: Load dram params from sdram config	2020-08-26 07:35:59 +00:00
northbridge	mrc_cache: Add mrc_cache fetch functions to support non-x86 platforms	2020-08-24 23:30:50 +00:00
security	drivers/spi/tpm: Enable long cr50 ready pulses for Tiger Lake systems	2020-08-20 19:34:46 +00:00
soc	soc/intel/tigerlake: Rename pch_init() code	2020-08-26 07:36:21 +00:00
southbridge	SMM: Validate more user-provided pointers	2020-08-21 07:51:07 +00:00
superio	src/superio: Drop unneeded empty lines	2020-08-24 09:14:42 +00:00
vendorcode	vc/amd/agesa/f15tn: add DDR1866_FREQUENCY to DdrMaxRateTab table	2020-08-26 07:30:44 +00:00
Kconfig	Kconfig: Update ASan config options	2020-08-21 07:42:21 +00:00