Brandon Breitenstein 135eae91d5 soc/intel/apollolake: Implement stage cache to improve resume time ... This patch enables stage cache to save ~40ms during S3 resume. It saves ramstage in the stage cache and restores it on resume so that ramstage does not have to reinitialize during the resume flow. Stage cache functionality is added to postcar stage since ramstage is called from postcar. BUG=chrome-os-partner:56941 BRANCH=none TEST=built for Reef and tested ramstage being cached Change-Id: I1551fd0faca536bd8c8656f0a8ec7f900aae1f72 Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/16833 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>		2016-10-07 18:18:14 +02:00
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broadcom/cygnus	soc/broadcom/cygnus/ddr_init.c: Correct typo in POWER ON and POWER OK.	2016-08-31 20:23:34 +02:00
dmp/vortex86ex	src/soc: Capitalize CPU, ACPI, RAM and ROM	2016-07-31 19:27:53 +02:00
imgtec/pistachio	drivers/uart: Use uart_platform_refclk for all UART models	2016-05-09 18:45:44 +02:00
intel	soc/intel/apollolake: Implement stage cache to improve resume time	2016-10-07 18:18:14 +02:00
marvell	soc/marvell/mvmap2315: Add DDR driver	2016-09-13 17:03:53 +02:00
mediatek/mt8173	src/soc: Add required space before opening parenthesis '('	2016-08-31 20:09:42 +02:00
nvidia	Makefiles: update cbfs types from bare numbers to values	2016-09-21 09:36:11 +02:00
qualcomm	soc/qualcomm/ipq40xx: Fix GPIO pull up config.	2016-10-07 17:55:19 +02:00
rdc/r8610	rdc/r8610: Move to src/soc	2016-05-05 20:08:58 +02:00
rockchip	rockchip/rk3399: Actually remove big CPU initialization from bootblock	2016-10-07 17:55:09 +02:00
samsung	src/soc: Capitalize CPU, ACPI, RAM and ROM	2016-07-31 19:27:53 +02:00
ucb/riscv	soc/ucb/riscv: select BOOTBLOCK_CONSOLE	2016-08-15 18:24:42 +02:00