Aaron Durbin 139314bffd mainboard/google/bolt: remove unobtainable mainboard ... The bolt board was a proof of concept device that has never made it out in the wild. Moreover, I don't think any of these boards exist any longer. Change-Id: I5ca055d448659a2b8e2eafcfc2114a6b8f8a56a4 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15901 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>		2016-07-27 21:25:06 +02:00
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acpi	arch/x86: provide common Intel ACPI hardware definitions	2016-07-15 08:31:21 +02:00
arch	arch/x86: Add bootblock and postcar support for SOC MTRR access	2016-07-27 13:50:39 +02:00
commonlib	cbmem: share additional time stamps IDs	2016-07-20 22:09:24 +02:00
console	console/post: be explicit about conditional cmos_post_log() compiling	2016-05-25 18:04:11 +02:00
cpu	cpu/x86: Support CPUs without rdmsr/wrmsr instructions	2016-07-27 13:50:11 +02:00
device	device: include devicetree in bootblock stage	2016-07-27 00:40:05 +02:00
drivers	cpu/x86: Support CPUs without rdmsr/wrmsr instructions	2016-07-27 13:50:11 +02:00
ec	chromeec: Use CHROMEEC_SOURCE with fallback instead of hardcoding path	2016-07-27 17:25:49 +02:00
include	cpu/x86: Support CPUs without rdmsr/wrmsr instructions	2016-07-27 13:50:11 +02:00
lib	lib: Don't require ULZMA compression for postcar	2016-07-26 04:53:33 +02:00
mainboard	mainboard/google/bolt: remove unobtainable mainboard	2016-07-27 21:25:06 +02:00
northbridge	nb/intel/x4x: Fix CAS latency detection and max memory detection	2016-07-27 11:40:33 +02:00
soc	soc/intel/apollolake: Disable monitor mwait	2016-07-27 19:36:01 +02:00
southbridge	timestamp: Drop duplicate TS_END_ROMSTAGE entries	2016-07-21 15:36:00 +02:00
superio	sio/winbond/w83667hg-a: Add pinmux defines for UART B	2016-05-29 19:34:54 +02:00
vendorcode	Rename VB_SOURCE to VBOOT_SOURCE for increased clarity	2016-07-27 17:26:05 +02:00
Kconfig	src/lib: Enable display of cbmem during romstage and postcar	2016-07-26 01:18:09 +02:00