Lijian Zhao a5b88e442b intel/cannonlake_rvp: Clean up GPIO programming ... Since we move from cannonlake U DDR 4 platform to cannonlake U LPDDR4 platform, it is also critical to revisit the GPIO settings as they are different. Remove unused GPIO setting for old platform, and clean up the native function definition. PAD_CFG_NF can only select NF1,NF2 ..., set to GPIO mode is illegal. TEST=Boot up in chromeos successfully. Change-Id: I0022b791bd8459ea2afdcd0241b603ce81408785 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/22326 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>		2017-11-07 21:05:27 +00:00
..
spd	intel/cannonlake_rvp: Modify memory parameters to support LP4 board	2017-10-16 15:23:37 +00:00
variants	intel/cannonlake_rvp: Clean up GPIO programming	2017-11-07 21:05:27 +00:00
acpi_tables.c	mainboard/intel/cannonlake_rvp: Add dummy DSDT table	2017-09-13 03:09:31 +00:00
board_info.txt
bootblock.c	src/mainboard/intel/cannonlake: Add gpio support for cannonlake	2017-08-23 15:53:10 +00:00
chromeos.c	src/mainboard/intel/cannonlake: Add gpio support for cannonlake	2017-08-23 15:53:10 +00:00
chromeos.fmd	mainboard/intel/cannonlake: Add ec entry into flashmap	2017-09-15 21:36:14 +00:00
dsdt.asl	soc/intel/cannonlake: Add platform.asl	2017-10-20 20:52:46 +00:00
Kconfig	mainboard/intel/cannonlake_rvp: Add smi support in board	2017-10-03 20:23:47 +00:00
Kconfig.name	intel/cannonlake_rvp: Update board name	2017-10-20 20:52:50 +00:00
mainboard.c	mainboard/intel/cannonlake_rvp: Enable variant gpio configuration	2017-10-24 15:54:14 +00:00
Makefile.inc	mainboard/intel/cannonlake_rvp: Enable variant gpio configuration	2017-10-24 15:54:14 +00:00
romstage.c	intel/cannonlake_rvp: Modify memory parameters to support LP4 board	2017-10-16 15:23:37 +00:00
smihandler.c	mainboard/intel/cannonlake_rvp: Add smi support in board	2017-10-03 20:23:47 +00:00