coreboot-kgpe-d16/src/mainboard/google/veyron_speedy
jinkun.hong 19ee1569f6 veyron: The ODT function is disabled for LPDDR3
We found that we should better keep ODT off for LPDDR3 on our boards.

BRANCH=veyron
BUG=chrome-os-partner:37346
TEST=Boot veyron_speedy normal

Change-Id: Id158c88769cf7ed1a5127cd09bad679a2f5e6a01
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0d85725a6faedb5bdbe8731991c225c31f138599
Original-Change-Id: Iebb8e74706756508dd56b85ad87baad48893c619
Original-Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com>
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/255381
Reviewed-on: http://review.coreboot.org/9830
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21 08:19:00 +02:00
..
sdram_inf veyron: The ODT function is disabled for LPDDR3 2015-04-21 08:19:00 +02:00
board.h veyron: move setup_chromeos_gpios() prototype to board.h 2015-04-17 09:24:13 +02:00
boardid.c
bootblock.c Kconfig: rename CONSOLE_SERIAL_UART to DRIVERS_UART 2015-04-20 18:43:36 +02:00
chromeos.c veyron: Add "backlight" GPIO to coreboot table 2015-04-15 16:54:07 +02:00
devicetree.cb rk3288: support edp HPD function 2015-04-15 22:13:40 +02:00
Kconfig Kconfig: rename CONSOLE_SERIAL_UART to DRIVERS_UART 2015-04-20 18:43:36 +02:00
Kconfig.name kconfig: automatically include mainboards 2015-04-18 08:31:08 +02:00
mainboard.c chromeos: Provide common watchdog reboot support 2015-04-17 09:56:49 +02:00
Makefile.inc
memlayout.ld
reset.c
romstage.c rk3288: detect sdram size at runtime 2015-04-17 09:26:09 +02:00
sdram_configs.c veyron: Sync up SDRAM configurations 2015-04-21 08:18:32 +02:00