Sumeet R Pawnikar 1a62150709 soc/intel/tigerlake: Set power limits for Tiger Lake Y-SKU ... Set power limits in devicetree for Tiger Lake Y-SKU based volteer variant boards. BUG=b:152639350 BRANCH=None TEST=Built and tested power limits on volteer variant board. Change-Id: If4f1226473b48365e5962df9fff29910c99007fc Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43607 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2020-07-25 00:07:36 +00:00
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acpi	src: Use ACPI macros	2020-07-21 18:26:47 +00:00
arch	src: Make HAVE_CF9_RESET set the FADT reset register	2020-07-20 13:23:13 +00:00
commonlib	src: Remove unused 'include <stdint.h>	2020-07-14 16:11:10 +00:00
console
cpu	cpu/intel/model_1067x: Drop <cpu/x86/mp.h> include	2020-07-14 16:15:09 +00:00
device	device/pci_device.c: Do not complain about disabled devices	2020-07-24 23:12:07 +00:00
drivers	drivers/intel/gma/Kconfig: Avoid dependency hell when ignoring straps	2020-07-20 17:13:22 +00:00
ec	ec/system76_ec: add support for System76 EC	2020-07-23 09:30:22 +00:00
include	soc/intel/tigerlake: Update Tiger Lake SA IDs	2020-07-25 00:07:20 +00:00
lib	src: Remove unused 'include <types.h>'	2020-07-14 16:10:17 +00:00
mainboard	soc/intel/tigerlake: Set power limits for Tiger Lake Y-SKU	2020-07-25 00:07:36 +00:00
northbridge	nb/intel/sandybridge: Put host bridge registers into its own file	2020-07-24 23:19:36 +00:00
security	security/intel/stm: Add missing <stdbool.h>	2020-07-21 20:04:12 +00:00
soc	soc/intel/tigerlake: Set power limits for Tiger Lake Y-SKU	2020-07-25 00:07:36 +00:00
southbridge	nb/intel/ironlake: Move southbridge code to ibexpeak	2020-07-24 14:29:36 +00:00
superio	superio/common: Avoid NULL pointer dereference	2020-07-24 21:21:09 +00:00
vendorcode	vc/amd/fsp/picasso: update UPD header	2020-07-24 20:29:11 +00:00
Kconfig	arch/x86: Remove RELOCATABLE_RAMSTAGE	2020-07-06 06:17:47 +00:00