coreboot-kgpe-d16/src/northbridge/intel
Angel Pons 1be9f5841d haswell: Introduce ENABLE_DDR_2X_REFRESH Kconfig option
This Kconfig symbol allows doubling the memory's refresh rate, assuming
that the MRC actually cares about it. It is disabled by default except
on the mainboards which explicitly enabled this setting in `pei_data`.

Change-Id: I6318dad0350d1c506c67f9d117d0ae8dad871281
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43122
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2020-07-12 10:08:09 +00:00
..
e7505 device/smbus_host: Declare common early SMBus prototypes 2020-06-22 11:53:31 +00:00
gm45 nb/intel/gm45/acpi/gm45.asl: Drop dead code 2020-07-09 23:53:40 +00:00
haswell haswell: Introduce ENABLE_DDR_2X_REFRESH Kconfig option 2020-07-12 10:08:09 +00:00
i440bx nb/intel/i440bx: Add PMCR register to ACPI code 2020-07-06 06:27:36 +00:00
i945 nb/intel/i945: Drop dead code 2020-07-11 11:19:27 +00:00
ironlake nb/intel/ironlake/raminit.c: Drop dead code 2020-07-09 23:47:13 +00:00
pineview nb/intel/pineview/acpi: Remove unmatched comment start 2020-07-08 22:10:21 +00:00
sandybridge nb/intel/sandybridge/gma.c: Remove useless if condition 2020-06-22 12:18:53 +00:00
x4x nb/intel/x4x/acpi: Use ASL 2.0 syntax 2020-07-08 22:07:10 +00:00