d9351099ef
Add SPI driver code for the legacy SPI flash controller. Enable erase and write support allowing coreboot to save non-volatile data into the SPI flash. TEST=Build and run on Galileo Gen2. Change-Id: I8f38c955d7c42a1e58728c728d0cecc36556de5c Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/20231 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
113 lines
2.8 KiB
C
113 lines
2.8 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2017 Intel Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/io.h>
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#include <console/console.h>
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#include <soc/spi.h>
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const char *spi_opcode_name(int opcode)
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{
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const char *op_name;
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switch (opcode) {
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default:
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op_name = "Unknown";
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break;
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case 1:
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op_name = "Write Status";
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break;
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case 2:
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op_name = "Page Program";
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break;
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case 3:
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op_name = "Read Data";
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break;
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case 5:
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op_name = "Read Status";
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break;
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case 6:
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op_name = "Write Data Enable";
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break;
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case 0x0b:
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op_name = "Fast Read";
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break;
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case 0x20:
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op_name = "Erase 4 KiB";
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break;
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case 0x50:
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op_name = "Write Status Enable";
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break;
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case 0x9f:
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op_name = "Read ID";
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break;
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case 0xd8:
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op_name = "Erase 64 KiB";
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break;
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}
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return op_name;
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}
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void spi_display(volatile struct flash_ctrlr *ctrlr)
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{
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int index;
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int opcode;
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const char *op_name;
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int prefix;
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int status;
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int type;
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/* Display the prefixes */
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printk(BIOS_DEBUG, "Prefix Table\n");
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for (index = 0; index < 2; index++) {
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prefix = ctrlr->prefix[index];
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op_name = spi_opcode_name(prefix);
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printk(BIOS_DEBUG, " %d: 0x%02x (%s)\n", index, prefix,
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op_name);
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}
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/* Display the opcodes */
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printk(BIOS_DEBUG, "Opcode Menu\n");
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for (index = 0; index < 8; index++) {
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opcode = ctrlr->opmenu[index];
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type = (ctrlr->type >> (index << 1)) & 3;
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op_name = spi_opcode_name(opcode);
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printk(BIOS_DEBUG, " %d: 0x%02x (%s), %s%s\n", index, opcode,
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op_name,
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(type & SPITYPE_PREFIX) ? "Write" : "Read",
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(type & SPITYPE_ADDRESS) ? ", w/3 byte address" : "");
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}
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/* Display the BIOS base address */
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printk(BIOS_DEBUG, "0x%08x: BIOS Base Address\n", ctrlr->bbar);
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/* Display the protection ranges */
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printk(BIOS_DEBUG, "BIOS Protected Range Regsiters\n");
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for (index = 0; index < ARRAY_SIZE(ctrlr->pbr); index++) {
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status = ctrlr->pbr[index];
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printk(BIOS_DEBUG, " %d: 0x%08x: 0x%08x - 0x%08x %s\n",
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index, status,
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0xff000000 | (0x1000000 - CONFIG_ROM_SIZE)
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| ((status & SPIPBR_PRB) << SPIPBR_PRB_SHIFT),
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0xff800fff | (0x1000000 - CONFIG_ROM_SIZE)
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| (status & SPIPBR_PRL),
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(status & SPIPBR_WPE) ? "Protected" : "Unprotected");
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}
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/* Display locked status */
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status = ctrlr->status;
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printk(BIOS_DEBUG, "0x%04x: SPISTS, Tables %s\n", status,
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(status & SPISTS_CLD) ? "Locked" : "Unlocked");
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}
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