Philipp Hug 1ed082bc8b riscv: simplify timer interrupt handling ... Just disable the timer interrupt and notify supervisor. To receive another timer interrupt just set timecmp and enable machine mode timer interrupt again. TEST=Run linux on sifive unleashed Change-Id: I5d693f872bd492c9d0017b514882a4cebd5ccadd Signed-off-by: Philipp Hug <philipp@hug.cx> Reviewed-on: https://review.coreboot.org/29340 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>		2018-10-30 02:09:05 +00:00
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include	riscv: add physical memory protection (PMP) support	2018-10-11 10:56:54 +00:00
arch_timer.c	arch/riscv: provide a monotonic timer	2018-09-14 09:28:06 +00:00
boot.c	selfboot: remove bounce buffers	2018-10-11 17:42:41 +00:00
bootblock.S	arch/riscv: Update comment about mstatus initialization	2018-10-06 21:30:32 +00:00
fp_asm.S	riscv: update misaligned memory access exception handling	2018-09-10 15:03:58 +00:00
Kconfig	arch/riscv: provide a monotonic timer	2018-09-14 09:28:06 +00:00
Makefile.inc	riscv: add physical memory protection (PMP) support	2018-10-11 10:56:54 +00:00
mcall.c	riscv: update mtime initialization	2018-09-10 15:03:08 +00:00
misaligned.c	src/arch/riscv/misaligned.c: Fix an off-by-one error when loading the opcode	2018-10-30 02:07:58 +00:00
misc.c	arch/riscv: provide a monotonic timer	2018-09-14 09:28:06 +00:00
payload.S	arch/riscv: Pass the bootrom-provided FDT to the payload	2018-02-20 20:46:12 +00:00
pmp.c	riscv: add physical memory protection (PMP) support	2018-10-11 10:56:54 +00:00
ramstage.S	arch/riscv: Update comment about mstatus initialization	2018-10-06 21:30:32 +00:00
stages.c	arch/riscv: Pass the bootrom-provided FDT to the payload	2018-02-20 20:46:12 +00:00
tables.c	lib: add common write_tables() implementation	2016-04-21 20:49:05 +02:00
trap_handler.c	riscv: simplify timer interrupt handling	2018-10-30 02:09:05 +00:00
trap_util.S	arch/riscv: Align trap_entry to 4 bytes, as required by spec	2018-02-20 20:44:43 +00:00
virtual_memory.c	riscv: don't write to mstatus.XS	2018-09-16 08:36:10 +00:00