coreboot-kgpe-d16/src/cpu/intel/model_6ex
Stefan Reinauer 0db6820b10 Synchronize rdtsc instructions
The CPU can arbitrarily reorder calls to rdtsc, significantly
reducing the precision of timing using the CPUs time stamp counter.
Unfortunately the method of synchronizing rdtsc is different
on AMD and Intel CPUs. There is a generic method, using the cpuid
instruction, but that uses up a lot of registers, and is very slow.
Hence, use the correct lfence/mfence instructions (for CPUs that
we know support it)

Change-Id: I17ecb48d283f38f23148c13159aceda704c64ea5
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1422
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2012-08-09 00:38:39 +02:00
..
cache_as_ram.inc Intel cpus: Extend cache to cover complete Flash Device 2012-07-04 14:47:53 +02:00
Kconfig Synchronize rdtsc instructions 2012-08-09 00:38:39 +02:00
Makefile.inc Intel cpus: Include CAR from socket 2012-03-17 09:38:31 +01:00
microcode-1624-m206e839.h Use the microcode files as created by the new microcode update script. (Fixes some whitespace and gets in new time stamps). 2010-05-26 16:54:33 +00:00
microcode-1729-m206ec54.h Use the microcode files as created by the new microcode update script. (Fixes some whitespace and gets in new time stamps). 2010-05-26 16:54:33 +00:00
microcode-1869-m806ec59.h Use the microcode files as created by the new microcode update script. (Fixes some whitespace and gets in new time stamps). 2010-05-26 16:54:33 +00:00
model_6ex_init.c Revert "Use broadcast SIPI to startup siblings" 2012-07-31 06:46:02 +02:00