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Aaron Durbin 1fef1f5177 haswell: reserve default SMRAM space
Currently the OS is free to use the memory located at the default
SMRAM space because it is not marked reserved in the e820. This can
lead to memory corruption on S3 resume because SMM setup doesn't save
this range before using it to relocate SMRAM.

Resulting tables:

	coreboot memory table:
	 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
	 1. 0000000000001000-000000000002ffff: RAM
	 2. 0000000000030000-000000000003ffff: RESERVED
	 3. 0000000000040000-000000000009ffff: RAM
	 4. 00000000000a0000-00000000000fffff: RESERVED
	 5. 0000000000100000-0000000000efffff: RAM
	 6. 0000000000f00000-0000000000ffffff: RESERVED
	 7. 0000000001000000-00000000acebffff: RAM
	 8. 00000000acec0000-00000000acffffff: CONFIGURATION TABLES
	 9. 00000000ad000000-00000000af9fffff: RESERVED
	10. 00000000f0000000-00000000f3ffffff: RESERVED
	11. 00000000fed10000-00000000fed19fff: RESERVED
	12. 00000000fed84000-00000000fed84fff: RESERVED
	13. 0000000100000000-000000018f5fffff: RAM

	e820 map has 13 items:
	  0: 0000000000000000 - 0000000000030000 = 1 RAM
	  1: 0000000000030000 - 0000000000040000 = 2 RESERVED
	  2: 0000000000040000 - 000000000009f400 = 1 RAM
	  3: 000000000009f400 - 00000000000a0000 = 2 RESERVED
	  4: 00000000000f0000 - 0000000000100000 = 2 RESERVED
	  5: 0000000000100000 - 0000000000f00000 = 1 RAM
	  6: 0000000000f00000 - 0000000001000000 = 2 RESERVED
	  7: 0000000001000000 - 00000000acec0000 = 1 RAM
	  8: 00000000acec0000 - 00000000afa00000 = 2 RESERVED
	  9: 00000000f0000000 - 00000000f4000000 = 2 RESERVED
	  10: 00000000fed10000 - 00000000fed1a000 = 2 RESERVED
	  11: 00000000fed84000 - 00000000fed85000 = 2 RESERVED
	  12: 0000000100000000 - 000000018f600000 = 1 RAM

Booted and checked e820 as well as coreboot table information.

Change-Id: Ie4985c748b591bf8c0d6a2b59549b698c9ad6cfe
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2688
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-15 16:58:37 +01:00
3rdparty@dac1a18d18 Eagleheights DSDT: Grant OS control through OSC 2013-03-13 23:44:00 +01:00
documentation sconfig: rename lapic_cluster -> cpu_cluster 2013-02-14 07:07:20 +01:00
payloads libpayload: add support for vboot_handoff 2013-03-14 04:57:03 +01:00
src haswell: reserve default SMRAM space 2013-03-15 16:58:37 +01:00
util GPLv2 notice: Unify all files to just use one space in »MA 02110-1301« 2013-03-01 10:16:08 +01:00
.gitignore add a few entries to .gitignore 2013-01-10 22:51:20 +01:00
.gitmodules Add 3rdparty as submodule 2012-05-01 00:08:37 +02:00
.gitreview add .gitreview 2012-11-01 23:13:39 +01:00
COPYING update license template. 2006-08-12 22:03:36 +00:00
Makefile build system: Retire REQUIRES_BLOB 2013-02-19 11:00:41 +01:00
Makefile.inc x86: SMM Module Support 2013-03-14 05:01:50 +01:00
README Update README with newer version of the text from the web page 2011-06-15 10:16:33 +02:00

README

-------------------------------------------------------------------------------
coreboot README
-------------------------------------------------------------------------------

coreboot is a Free Software project aimed at replacing the proprietary BIOS
(firmware) found in most computers.  coreboot performs a little bit of
hardware initialization and then executes additional boot logic, called a
payload.

With the separation of hardware initialization and later boot logic,
coreboot can scale from specialized applications that run directly
firmware, run operating systems in flash, load custom
bootloaders, or implement firmware standards, like PC BIOS services or
UEFI. This allows for systems to only include the features necessary
in the target application, reducing the amount of code and flash space
required.

coreboot was formerly known as LinuxBIOS.


Payloads
--------

After the basic initialization of the hardware has been performed, any
desired "payload" can be started by coreboot.

See http://www.coreboot.org/Payloads for a list of supported payloads.


Supported Hardware
------------------

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

 * http://www.coreboot.org/Supported_Motherboards
 * http://www.coreboot.org/Supported_Chipsets_and_Devices


Build Requirements
------------------

 * gcc / g++
 * make

Optional:

 * doxygen (for generating/viewing documentation)
 * iasl (for targets with ACPI support)
 * gdb (for better debugging facilities on some targets)
 * ncurses (for 'make menuconfig')
 * flex and bison (for regenerating parsers)


Building coreboot
-----------------

Please consult http://www.coreboot.org/Build_HOWTO for details.


Testing coreboot Without Modifying Your Hardware
------------------------------------------------

If you want to test coreboot without any risks before you really decide
to use it on your hardware, you can use the QEMU system emulator to run
coreboot virtually in QEMU.

Please see http://www.coreboot.org/QEMU for details.


Website and Mailing List
------------------------

Further details on the project, a FAQ, many HOWTOs, news, development
guidelines and more can be found on the coreboot website:

  http://www.coreboot.org

You can contact us directly on the coreboot mailing list:

  http://www.coreboot.org/Mailinglist


Copyright and License
---------------------

The copyright on coreboot is owned by quite a large number of individual
developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL).
Some files are licensed under the "GPL (version 2, or any later version)",
and some files are licensed under the "GPL, version 2". For some parts, which
were derived from other projects, other (GPL-compatible) licenses may apply.
Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.