coreboot-kgpe-d16/src/northbridge/intel/x4x
Arthur Heymans c82950bf79 nb/intel/x4x: Use parallel MP init
Use parallel MP init code to initialize all AP's.

Also remove guards around CPU code where all platforms now use
parallel MP init.

This also removes the code required on lapic init path for
model_6fx, model_1017x and model_f4x as all platforms now use the
parallel MP code.

Tested on Intel DG41WV, shaves off about 90ms on a quad core.

Change-Id: Id5a2729f5bf6b525abad577e63d7953ae6640921
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/25601
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-23 14:47:53 +00:00
..
acpi sb/intel/i82801{g,j}x: Automatically generate ACPI PIRQ tables 2018-06-29 07:45:30 +00:00
acpi.c device: Use pcidev_on_root() 2019-01-06 01:17:54 +00:00
bootblock.c nb/intel/x4x: Fix issues found by checkpatch.pl 2017-03-21 20:11:15 +01:00
chip.h
dq_dqs.c src: Remove unneeded whitespace 2018-10-23 15:52:09 +00:00
early_init.c src: Remove unneeded include <cbmem.h> 2018-11-16 10:56:47 +00:00
gma.c nb/intel/x4x: Remove spurious pcidev_on_root() usage 2019-01-13 14:01:19 +00:00
iomap.h nb/intel/x4x: Fix issues found by checkpatch.pl 2017-03-21 20:11:15 +01:00
Kconfig nb/intel/x4x: Use parallel MP init 2019-01-23 14:47:53 +00:00
Makefile.inc nb/intel/x4x: Switch to POSTCAR_STAGE 2018-06-05 07:49:20 +00:00
northbridge.c nb/intel/x4x: Use parallel MP init 2019-01-23 14:47:53 +00:00
ram_calc.c nb/intel/x4x: Use common code for SMM in TSEG 2018-12-03 10:18:56 +00:00
raminit.c mb: Move timestamp_add_now to northbridge x4x 2019-01-10 09:53:51 +00:00
raminit_ddr23.c northbridge: Remove unneeded include <pc80/mc146818rtc.h> 2018-12-18 13:49:31 +00:00
raminit_tables.c src: Fix typo 2018-08-10 21:25:53 +00:00
rcven.c nb/intel/x4x/rcven.c: Change the verbosity of some messages 2018-04-17 10:41:57 +00:00
x4x.h nb/intel/x4x: Use common code for SMM in TSEG 2018-12-03 10:18:56 +00:00