Arthur Heymans 2437fe9dfa sb/intel/i82801gx: Move CIR init to a common place ... Some boards with the G41 chipset lacked programming CIR, so this change add that to those boards too. Change-Id: Ia10c050785170fc743f7aef918f4849dbdd6840e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>		2019-10-11 12:21:25 +00:00
..
acpi	{mb,nb/pineview}/*.asl: Remove unneeded include i82801gx.h	2019-03-13 04:17:46 +00:00
acpi.c
bootblock.c	nb/intel/pineview: Move to C_ENVIRONMENT_BOOTBLOCK	2019-05-25 15:49:27 +00:00
chip.h	src/northbridge: Add and update license headers	2018-05-29 22:36:37 +00:00
early_init.c	sb/intel/i82801gx: Move CIR init to a common place	2019-10-11 12:21:25 +00:00
gma.c	src/northbridge: Add missing 'include <types.h>'	2019-05-29 20:28:27 +00:00
iomap.h	Remove DEFAULT_PCIEXBAR alias	2019-03-06 11:54:17 +00:00
Kconfig	nb/intel/pineview/Kconfig: Remove romcc leftover	2019-10-10 15:38:45 +00:00
Makefile.inc	northbridge/intel: Rename ram_calc.c to memmap.c	2019-08-07 05:42:15 +00:00
memmap.c	intel/smm/gen1: Use smm_subregion()	2019-08-28 22:51:27 +00:00
northbridge.c	intel/smm/gen1: Rename header file	2019-08-15 06:53:52 +00:00
pineview.h	intel/pci: Utilise pci_def.h for PCI_BRIDGE_CONTROL	2019-10-01 01:54:08 +00:00
raminit.c	sb/intel/nm10: Fix enabling HPET	2019-10-06 22:11:32 +00:00
raminit.h
romstage.c	soc/intel: Use common romstage code	2019-08-26 21:08:41 +00:00