coreboot-kgpe-d16/src
Xiang Wang 26f725efc2 riscv: add support to block smp in each stage
Each stage performs some basic initialization (stack, HLS etc) and then
call smp_pause to enter the single-threaded state. The main work of each
stage is executed in a single-threaded state, and the multi-threaded
state is restored by call smp_resume while booting the next stage.

Change-Id: I8d508c3d0f65a022010e74f8edad7ad2cfdc7dee
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/29024
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Philipp Hug <philipp@hug.cx>
2018-11-05 09:03:50 +00:00
..
acpi
arch riscv: add support to block smp in each stage 2018-11-05 09:03:50 +00:00
commonlib src: Remove unneeded whitespace 2018-10-23 15:52:09 +00:00
console console: Set default loglevel to 8 (SPEW) for CONFIG_CHROMEOS 2018-10-18 12:50:41 +00:00
cpu amd: Fix non-local header treated as local 2018-11-05 09:00:26 +00:00
device src: Remove unneeded whitespace 2018-10-23 15:52:09 +00:00
drivers amd: Fix non-local header treated as local 2018-11-05 09:00:26 +00:00
ec ec/google/wilco: Add wake pin configuration 2018-11-02 16:07:01 +00:00
include src: Add missing include <stdint.h> 2018-11-01 11:25:07 +00:00
lib reset: Finalize move to new API 2018-10-31 15:29:42 +00:00
mainboard mb/google/poppy/variant/nocturne: add Nanya memory option 2018-11-05 09:03:11 +00:00
northbridge amd: Fix non-local header treated as local 2018-11-05 09:00:26 +00:00
security src: Add missing include <stdint.h> 2018-11-01 11:25:07 +00:00
soc riscv: add support smp_pause / smp_resume 2018-11-05 09:03:40 +00:00
southbridge amd: Fix non-local header treated as local 2018-11-05 09:00:26 +00:00
superio src: Add missing include <stdint.h> 2018-11-01 11:25:07 +00:00
vendorcode sb/intel/lynxpoint: Include <stdint.h> to fix compilation errors 2018-11-01 22:24:24 +00:00
Kconfig reset: Finalize move to new API 2018-10-31 15:29:42 +00:00