li feng 2cf9d3883c soc/intel/tigerlake: Support ISH ... Add ACPI Object for ISH SSDT Enable/disable ISH based on devicetree BRANCH=none BUG=b:145946347 TEST=boot to OS with TGL RVP UP3 Signed-off-by: Hu, Hebo <hebo.hu@intel.com> Signed-off-by: li feng <li1.feng@intel.com> Change-Id: I30f4d936ece139cf67640e6df6a9f47579f87bca Reviewed-on: https://review.coreboot.org/c/coreboot/+/39480 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>		2020-03-16 14:46:31 +00:00
..
apollolake	soc/intel/*/smihandler: Only compile in TCO SMI handler if needed	2020-03-12 21:36:20 +00:00
baytrail	src: capitalize 'PCIe'	2020-03-04 15:43:30 +00:00
braswell	soc/intel/braswell/chip.h: Include smbios.h for Type9 Entries	2020-03-09 11:03:41 +00:00
broadwell	src: capitalize 'PCIe'	2020-03-04 15:43:30 +00:00
cannonlake	soc/intel/*/smihandler: Only compile in TCO SMI handler if needed	2020-03-12 21:36:20 +00:00
common	soc/intel/Kconfig: Avoid specifying dedicated chipset name	2020-03-15 13:12:05 +00:00
denverton_ns	soc/intel/dnv: Set INT_LINE accouting for PIRQ routing & swizzling	2020-03-10 20:45:53 +00:00
icelake	soc/intel/icelake: Re-flow comment for 96 characters	2020-03-15 12:57:02 +00:00
quark	soc/intel: Add get_pmbase	2020-02-04 18:54:01 +00:00
skylake	soc/intel/*/smihandler: Only compile in TCO SMI handler if needed	2020-03-12 21:36:20 +00:00
tigerlake	soc/intel/tigerlake: Support ISH	2020-03-16 14:46:31 +00:00
xeon_sp	soc/intel/xeon-sp,mb/ocp/tiogapass: Don't fake binaries	2020-03-10 11:52:45 +00:00
Kconfig	soc/intel/Kconfig: Avoid specifying dedicated chipset name	2020-03-15 13:12:05 +00:00