ee0b7ad683
It turned on some SKUs FSP hangs in Notify stage if IIO root ports are disabled after MemoryInit. To address that hide IIO root ports earlier in romstage. TEST=the patch was ran on affected HW and success was reported Change-Id: I6a2a405f729df14f46bcf34a24e66e8ba9415f9d Signed-off-by: Andrey Petrov <anpetrov@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35968 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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Intel Firmware Support Package (FSP)-specific documentation
This section contains documentation about Intel-FSP in public domain.
Bugs
As Intel doesn't even list known bugs, they are collected here until those are fixed. If possible a workaround is described here as well.
BroadwellDEFsp
-
IA32_FEATURE_CONTROL MSR is locked in FSP-M
- Release MR2
- Writing the MSR is required in ramstage for Intel TXT
- Workaround: none
- Issue on public tracker: Issue 10
-
FSP-S asserts if the thermal PCI device 00:1f.6 is disabled
- Release MR2
- FSP expects the PCI device to be enabled
- FSP expects BARs to be properly assigned
- Workaround: Don't disable this PCI device
- Issue on public tracker: Issue 13
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FSP Notify(EnumInitPhaseAfterPciEnumeration) hangs if 00:02.03/00:02.03 are hidden
- Release MR2
- Seems to get stuck on some SKUs only if hidden after MemoryInit
- Workaround: Hide before MemoryInit
- Issue on public tracker: Issue 35
KabylakeFsp
- MfgId and ModulePartNum in the DIMM_INFO struct are empty
- Release 3.7.1
- Those values are typically consumed by SMBIOS type 17
- Workaround: none
- Issue on public tracker: Issue 22
BraswellFsp
- Internal UART can't be disabled using PcdEnableHsuart*
- Release MR2
- Workaround: Disable internal UART manually after calling FSP
- Issue on public tracker: Issue 10