2871e0e78c
List of changes: 1. Add required SoC programming till ramstage 2. Include only required headers into include/soc 3. Add CPU, PCH and SA EDS document number and chapter number 4. Fill required FSP-S UPD to call FSP-S API Change-Id: I3394f585d66b14ece67cde9e45ffa1177406f35f Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
71 lines
1.7 KiB
C
71 lines
1.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* This file is created based on Intel Alder Lake Processor SA Datasheet
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* Document number: 619503
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* Chapter number: 3
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*/
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#include <device/device.h>
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#include <device/pci.h>
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#include <intelblocks/systemagent.h>
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#include <soc/iomap.h>
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#include <soc/systemagent.h>
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/*
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* SoC implementation
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*
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* Add all known fixed memory ranges for Host Controller/Memory
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* controller.
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*/
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void soc_add_fixed_mmio_resources(struct device *dev, int *index)
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{
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static const struct sa_mmio_descriptor soc_fixed_resources[] = {
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{ PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_SA_PCIEX_LENGTH,
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"PCIEXBAR" },
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{ MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" },
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{ DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" },
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{ EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR" },
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{ REGBAR, REG_BASE_ADDRESS, REG_BASE_SIZE, "REGBAR" },
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{ EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" },
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};
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sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources,
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ARRAY_SIZE(soc_fixed_resources));
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/* Add Vt-d resources if VT-d is enabled */
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if ((pci_read_config32(dev, CAPID0_A) & VTD_DISABLE))
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return;
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sa_add_fixed_mmio_resources(dev, index, soc_vtd_resources,
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ARRAY_SIZE(soc_vtd_resources));
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}
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/*
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* SoC implementation
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*
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* Perform System Agent Initialization during Ramstage phase.
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*/
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void soc_systemagent_init(struct device *dev)
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{
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/* Enable Power Aware Interrupt Routing */
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enable_power_aware_intr();
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/* Enable BIOS Reset CPL */
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enable_bios_reset_cpl();
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/* TODO: Add set_power_limits() */
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}
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uint32_t soc_systemagent_max_chan_capacity_mib(u8 capid0_a_ddrsz)
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{
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switch (capid0_a_ddrsz) {
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case 1:
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return 8192;
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case 2:
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return 4096;
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case 3:
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return 2048;
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default:
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return 65536;
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}
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}
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