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coreboot-kgpe-d16/src/soc/intel/alderlake
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Michael Niewöhner 310c7637da soc/intel: deduplicate ACPI timer emulation 
The code for enabling ACPI timer emulation is the same for the SoCs
SKL, CNL, ICL, TGL, JSL and EHL. Deduplicate it by moving it to
common code.

APL differs in not having the delay settings. However, the bits are
marked as "spare" and BWG mentions there are no "reserved bit checks
done". Thus, we can write them unconditionally without any effect.

Note: The ACPI timer emulation can only be used by SoCs with microcode
supporting CTC (Common Timer Copy) / ACPI timer emulation.

Change-Id: Ied4b312b6d53e80e71c55f4d1ca78a8cb2799793
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45951
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-28 21:28:19 +00:00
..
acpi soc/intel: Make use of common gfx.asl 2020-10-08 04:09:46 +00:00
bootblock soc/intel/alderlake: Rename pch_init() code 2020-09-10 05:26:46 +00:00
include/soc {cpu,soc}/intel: deduplicate cpu code 2020-10-24 09:46:45 +00:00
romstage soc/intel/alderlake/romstage: Skip GPIO configuration from FSP 2020-10-25 06:18:03 +00:00
acpi.c soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage 2020-10-03 12:15:22 +00:00
chip.c soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage 2020-10-03 12:15:22 +00:00
chip.h mb/*,soc/intel: drop the obsolete dt option speed_shift_enable 2020-10-26 06:51:42 +00:00
cpu.c soc/intel: deduplicate ACPI timer emulation 2020-10-28 21:28:19 +00:00
elog.c soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage 2020-10-03 12:15:22 +00:00
espi.c soc/intel/alderlake/ramstage: Fix compilation issue 2020-10-06 12:30:15 +00:00
finalize.c soc/intel/*: drop useless XTAL shutdown qualification code 2020-10-19 07:09:12 +00:00
fsp_params.c soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage 2020-10-03 12:15:22 +00:00
gpio.c soc/intel/alderlake: Add GPIOs for Alder Lake SOC 2020-09-27 03:03:25 +00:00
gspi.c soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage 2020-10-03 12:15:22 +00:00
i2c.c soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage 2020-10-03 12:15:22 +00:00
Kconfig soc/intel: convert XTAL frequency constant to Kconfig 2020-10-21 07:14:00 +00:00
lockdown.c soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage 2020-10-03 12:15:22 +00:00
Makefile.inc soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage 2020-10-03 12:15:22 +00:00
me.c soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage 2020-10-03 12:15:22 +00:00
meminit.c soc/intel/alderlake/romstage: Do initial SoC commit till romstage 2020-09-15 15:13:50 +00:00
p2sb.c soc/intel/alderlake/romstage: Do initial SoC commit till romstage 2020-09-15 15:13:50 +00:00
pmc.c soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage 2020-10-03 12:15:22 +00:00
pmutil.c soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage 2020-10-03 12:15:22 +00:00
reset.c Revert "soc/intel: Refactor do_global_reset() function" 2020-09-22 05:13:39 +00:00
smihandler.c soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage 2020-10-03 12:15:22 +00:00
smmrelocate.c soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage 2020-10-03 12:15:22 +00:00
soundwire.c soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage 2020-10-03 12:15:22 +00:00
spi.c soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage 2020-10-03 12:15:22 +00:00
systemagent.c soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage 2020-10-03 12:15:22 +00:00
uart.c soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage 2020-10-03 12:15:22 +00:00