Kyösti Mälkki ccb53e1817 binaryPI: Fix cache coherency use for AP CPUs ... The memory between _car_region_start .. _car_region_end has to be set up as WB in MTRRs for all the cores executing through bootblock, verstage and romstage. Otherwise global variables may fail on AP CPUs. Fixes combination of CBMEM_CONSOLE=y with SQUELCH_EARLY_SMP=n, which previously did not boot at all for some cases. Change-Id: I4abcec90c03046e32dafcf97d2f7228ca93c5549 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/26115 Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2019-02-14 15:16:19 +00:00
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amd	binaryPI: Fix cache coherency use for AP CPUs	2019-02-14 15:16:19 +00:00
cavium	vendorcode/{amd,cavium,intel}: Remove trailing whitespace	2019-01-17 14:52:33 +00:00
google	coreboot: check Cr50 PM mode on normal boot	2019-02-13 13:03:33 +00:00
intel	mb/intel/galileo: Drop the FSP1.1 option	2019-02-11 12:28:52 +00:00
siemens	src: Fix all Siemens copyrights	2017-11-07 12:33:51 +00:00
Makefile.inc	soc/cavium: Integrate BDK files into coreboot	2018-07-03 15:53:32 +00:00