Felix Held 338d670beb soc/amd/cezanne/Kconfig: select common PSP gen2 support ... Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic6068e8b9eb210ce4907fda09208e66e380842de Reviewed-on: https://review.coreboot.org/c/coreboot/+/50152 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>		2021-01-31 01:13:04 +00:00
..
include/soc	soc/amd/cezanne: add soc/cpu.h with CPUID define for Cezanne A0 stepping	2021-01-31 01:08:46 +00:00
aoac.c	soc/amd/cezanne: add AOAC support	2021-01-14 15:42:34 +00:00
bootblock.c	soc/amd/cezanne: add caching setup in bootblock	2020-12-13 22:18:03 +00:00
chip.c	soc/amd/cezanne: add use result of acpi_is_wakeup_s3() in FSP calls	2021-01-30 17:17:24 +00:00
chip.h	soc/amd/cezanne: add config.c and minimal chip.h	2020-12-06 19:05:47 +00:00
chipset.cb	soc/amd/cezzane: Add a minimal chipset tree	2021-01-11 07:42:12 +00:00
config.c	soc/amd/cezanne: add config.c and minimal chip.h	2020-12-06 19:05:47 +00:00
early_fch.c	soc/amd/cezanne: add AOAC support	2021-01-14 15:42:34 +00:00
fch.c	soc/amd/cezanne: add empty ramstage FCH support	2021-01-29 22:57:01 +00:00
fsp_params.c	soc,vendorcode/amd/cezanne: add basic FSP integration	2021-01-24 18:15:46 +00:00
fw.cfg	soc/amd/cezanne: Add PSP integration for cezanne	2021-01-24 18:09:19 +00:00
gpio.c	soc/amd/cezanne: add GPIO support	2020-12-18 17:20:56 +00:00
Kconfig	soc/amd/cezanne/Kconfig: select common PSP gen2 support	2021-01-31 01:13:04 +00:00
Makefile.inc	soc/amd/cezanne: add empty ramstage FCH support	2021-01-29 22:57:01 +00:00
reset.c	soc/amd/cezanne: add 0xcf9 reset	2020-12-11 17:44:42 +00:00
romstage.c	soc/amd/cezanne: add use result of acpi_is_wakeup_s3() in FSP calls	2021-01-30 17:17:24 +00:00
uart.c	soc/amd/cezanne,picasso/uart: remove unneeded struct name	2021-01-15 01:19:59 +00:00