Kevin Chiu 348a6d519c soc/intel/braswell: add USB2 PHY PERPORTRXISET UPD ... Adapted from Chromium commits 59938a0, 5a4ea6e, 88999de. Add UPD to config USB2 PERPORTRXISET for D-stepping BSW SoC. Ensure PerPortRXISet UPD offsets align with FSP. Ensure UPD values not defined in devicetree.cb are referred from *.dsc. Original-Change-Id: Ib0cdee47692e492a78c34e2dd192447b92253e35 Original-Change-Id: If0d8419d4c70864bd385b5699e0e6d1ec515d26a Original-Change-Id: I3a1d688282303e8c367620ac8bb3e2cba7ab3dcf Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Keith Tzeng <keith.tzeng@quantatw.com> Change-Id: I87eda6ea6688931f1a1b069c38ffc515398ad396 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21373 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>		2017-09-08 21:09:48 +00:00
..
acpi	soc/braswell: assign unique DMA request lines to I2C controllers	2017-06-09 16:56:47 +02:00
bootblock
include/soc	soc/intel/braswell: Add USB2 phy setting override	2017-09-08 21:09:19 +00:00
romstage
acpi.c	fsp/gop: Add running the GOP to the choice of gfx init	2017-06-08 14:58:29 +02:00
chip.c	soc/intel/braswell: add USB2 PHY PERPORTRXISET UPD	2017-09-08 21:09:48 +00:00
chip.h	soc/intel/braswell: add USB2 PHY PERPORTRXISET UPD	2017-09-08 21:09:48 +00:00
cpu.c	soc/intel/braswell: Fix most of the issues detected by checkpatch	2017-03-17 02:36:36 +01:00
elog.c
emmc.c
gfx.c
gpio.c
gpio_support.c
hda.c
iosf.c
Kconfig	soc/intel/braswell: select GENERIC_GPIO_LIB	2017-08-25 18:56:24 +00:00
lpc_init.c
lpe.c	soc/intel/braswell: Fix most of the issues detected by checkpatch	2017-03-17 02:36:36 +01:00
lpss.c
Makefile.inc	fsp/gop: Add running the GOP to the choice of gfx init	2017-06-08 14:58:29 +02:00
memmap.c
northcluster.c	soc/braswell: fix ACPI table by recollecting TOLM	2017-06-09 17:04:33 +02:00
pcie.c	soc/intel/braswell: Add int to unsigned	2017-03-17 02:36:16 +01:00
placeholders.c
pmutil.c
ramstage.c
sata.c
scc.c	soc/intel/braswell: Populate NVS SCC BAR1	2017-08-25 18:59:35 +00:00
sd.c
smihandler.c
smm.c
southcluster.c	soc/intel/braswell: Put SERIRQ in quiet mode	2017-08-25 18:59:51 +00:00
spi.c	Rename __attribute__((packed)) --> __packed	2017-07-13 19:45:59 +00:00
spi_loading.c
tsc_freq.c	soc/intel/braswell: Fix most of the issues detected by checkpatch	2017-03-17 02:36:36 +01:00
xhci.c	soc/intel/braswell: Fix most of the issues detected by checkpatch	2017-03-17 02:36:36 +01:00