Brandon Breitenstein df12d1923f soc/intel/apollolake: Update FSP Header files for version 146_30 ... Add new UPDs for Fspm and Fsps. Update headers to make new UPDs available for use. New UPDs enable various memory and trace funtionality options as well as support for zero sized IBB region. BUG=chrome-os-partner:55513 BRANCH=none TEST=built and tested with no regressions Change-Id: Id1573baaa306ed4fe4353df5f27e5963cb1a76e6 Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/15815 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>		2016-07-28 21:21:06 +02:00
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apollolake	soc/intel/apollolake: Update FSP Header files for version 146_30	2016-07-28 21:21:06 +02:00
baytrail	bootmode: Get rid of CONFIG_BOOTMODE_STRAPS	2016-07-28 00:36:22 +02:00
braswell	soc/intel/braswell: use common Intel ACPI hardware definitions	2016-07-15 08:32:09 +02:00
broadwell	soc/intel/broadwell: Use init_vbnv_cmos from vboot vbnv	2016-07-28 00:41:40 +02:00
common	intel/common: Add ASL code for DPTF	2016-07-28 20:09:58 +02:00
fsp_baytrail	soc/intel/fsp_baytrail: use common Intel ACPI hardware definitions	2016-07-15 08:33:03 +02:00
fsp_broadwell_de	soc/intel/fsp_broadwell_de: use common Intel ACPI hardware definitions	2016-07-15 08:32:35 +02:00
quark	cpu/x86: Support CPUs without rdmsr/wrmsr instructions	2016-07-27 13:50:11 +02:00
sch	intel/sch: Merge northbridge and southbridge in src/soc	2016-05-17 21:38:17 +02:00
skylake	intel/fsp1_1: Add C entry support to locate FSP Temp RAM Init	2016-07-28 05:29:46 +02:00