John Zhao 81547a7d05 soc/intel/alderlake: Add validity for TBT firmware authentication ... After Thunderbolt firmware is downloaded to IMR, its authentication validity needs to be checked. This change adds the TBT firmware IMR status register offset and its authentication valid bit for valid_tbt_auth function usage. BUG=b:188695995 TEST=Built coreboot image successfully. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I742a00b6b58c45c1261f06b06a94346ad0a74829 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54888 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2021-05-26 15:43:14 +00:00
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acpi	soc/intel/alderlake: Add handling of GPIO_COM3 in gpio.asl	2021-05-18 17:03:43 +00:00
bootblock	soc/intel/common: Add Alder Lake device IDs	2021-05-21 11:23:12 +00:00
include/soc	soc/intel/alderlake: Add validity for TBT firmware authentication	2021-05-26 15:43:14 +00:00
romstage	soc/intel/alderlake: Add CrashLog implementation for Intel ADL	2021-05-06 03:32:22 +00:00
spd	util: Add new memory part to LP4x list	2021-03-03 15:50:47 +00:00
acpi.c	soc/intel/alderlake: Use device ID from pci_devs header file	2021-04-26 08:27:54 +00:00
chip.c	soc/intel: Replace open-coded buffer length calculation	2021-04-21 14:21:44 +00:00
chip.h	soc/intel/alderlake: mb/intel/sm: Add tcss code	2021-05-18 10:09:04 +00:00
chipset.cb	soc/intel/alderlake: Add CrashLog implementation for Intel ADL	2021-05-06 03:32:22 +00:00
cpu.c	soc/intel/{adl,tgl,jsl}: Enable power button smi after BS_CHIPS_EXIT	2021-05-07 06:05:37 +00:00
crashlog.c	soc/intel/alderlake: Add CrashLog implementation for Intel ADL	2021-05-06 03:32:22 +00:00
dptf.c	soc/intel/alderlake: Add DPTF HIDs for Alder Lake SoC	2021-04-23 14:46:33 +00:00
elog.c	soc/intel/*: Update data types for variables holding PCH_DEVFN_* macros	2021-05-03 16:28:53 +00:00
espi.c	src: Match array format in function declarations and definitions	2021-05-13 18:34:38 +00:00
finalize.c
fsp_params.c	soc/intel/alderlake: mb/intel/sm: Add tcss code	2021-05-18 10:09:04 +00:00
gpio.c	soc/intel/alderlake: Add known GPIO virtual wire information	2021-05-14 08:58:07 +00:00
gspi.c
i2c.c
Kconfig	soc/intel/alderlake: Add CrashLog implementation for Intel ADL	2021-05-06 03:32:22 +00:00
lockdown.c
Makefile.inc	cpu/x86: Only include smm code if CONFIG_HAVE_SMI_HANDLER=y	2021-05-18 16:54:21 +00:00
me.c
meminit.c	soc/intel/alderlake: Update meminit code due to upd changes FSP 2147 onwards	2021-05-16 22:17:52 +00:00
p2sb.c
pcie_rp.c
pmc.c	soc/intel/{adl,tgl,jsl}: Enable power button smi after BS_CHIPS_EXIT	2021-05-07 06:05:37 +00:00
pmutil.c	soc/intel/*/pmutil.c: Align cosmetics across platforms	2021-02-24 11:34:42 +00:00
reset.c
smihandler.c	soc/intel/{adl,tgl,jsl}: Add smihandler_soc_disable_busmaster	2021-05-07 06:05:18 +00:00
soundwire.c
spi.c
systemagent.c	soc/intel/alderlake: add processor power limits control support	2021-03-28 16:08:02 +00:00
uart.c	soc/intel/*: drop UART pad configuration from common code	2021-03-12 08:48:03 +00:00
xhci.c	soc/intel/alderlake: Add soc_get_xhci_usb_info() for elog support	2021-02-24 11:27:51 +00:00